 Yehowshua Immanuel
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a76d6e24ec
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correct behavior of R type in execute
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2025-03-13 16:26:03 -04:00 |
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Yehowshua Immanuel
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4428f7f196
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fixed execution of R type instructions
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2025-03-13 14:31:38 -04:00 |
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Yehowshua Immanuel
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7066df0936
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Grok mostly wrote execute - will test later...
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2025-03-10 23:00:23 -04:00 |
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Yehowshua Immanuel
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69f5cdee6a
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added needed context and getting ready to implement execute
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2025-03-10 22:26:38 -04:00 |
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Yehowshua Immanuel
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b95b2b962a
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read seemingly complete
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2025-03-10 17:46:06 -04:00 |
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Yehowshua Immanuel
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ad751a5039
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read is getting there...
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2025-03-10 17:22:51 -04:00 |
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Yehowshua Immanuel
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171fcece98
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reduce debug in sim and add PREFIX to makefile
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2025-03-07 22:04:40 -05:00 |
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Yehowshua Immanuel
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63a73d3f71
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now fetching from ram correctly as ram is 32 bit word not byte indexed
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2025-03-07 21:41:46 -05:00 |
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Yehowshua Immanuel
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3f50fe32f8
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still compiling after refactoring field types
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2025-03-07 20:31:41 -05:00 |
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Yehowshua Immanuel
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73d5e1204c
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stopping point before re-factoring decoder types
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2025-03-07 18:41:55 -05:00 |
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Yehowshua Immanuel
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6b81cd28ee
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working on adding read stage
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2025-03-07 12:09:08 -05:00 |
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Yehowshua Immanuel
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4cc8c8d430
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Forgot to replace $ operator in Uart.hs
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2025-03-06 08:44:28 -05:00 |
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Yehowshua Immanuel
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0792bf3c7d
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Replacing $ operator with more readable |> operator
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2025-03-06 08:41:00 -05:00 |
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Yehowshua Immanuel
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2b1c486c17
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created Decode result
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2025-03-05 09:04:54 -05:00 |
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Yehowshua Immanuel
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7f7ba49ee1
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prune more warnings and re-org Decode files a bit
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2025-03-05 00:09:04 -05:00 |
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Yehowshua Immanuel
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67b44dedc0
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clean up warnings a bit
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2025-03-04 23:54:30 -05:00 |
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Yehowshua Immanuel
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30650b870c
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replace/update relevant fetch types and functions
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2025-03-04 23:43:35 -05:00 |
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Yehowshua Immanuel
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eb79210863
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now using bus and new FetchResult type
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2025-03-04 23:37:33 -05:00 |
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Yehowshua Immanuel
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4729d79b23
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refactoring towards types that can handle exceptions between stages
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2025-03-04 23:05:52 -05:00 |
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Yehowshua Immanuel
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d7d698a28c
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save progress before switching to new bus architecture
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2025-03-04 08:12:59 -05:00 |
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Yehowshua Immanuel
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88ec010f98
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initial support for exceptions
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2025-03-02 23:12:02 -05:00 |
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Yehowshua Immanuel
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5552ad3d4a
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bus architecture re-built I think
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2025-02-26 13:05:02 -05:00 |
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Yehowshua Immanuel
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c8b192cade
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prep for notable re-org
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2025-02-26 02:24:23 -05:00 |
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Yehowshua Immanuel
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024115e389
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Uart now has correct write implementation presumably
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2025-02-26 01:51:33 -05:00 |
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Yehowshua Immanuel
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8d5cd862ab
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more progress on UART read
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2025-02-25 23:47:00 -05:00 |
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Yehowshua Immanuel
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7265728932
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read getting closer to being done
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2025-02-25 19:09:37 -05:00 |
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Yehowshua Immanuel
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1f9bd2f015
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hopefully progressing to a more scalable bus architecture
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2025-02-25 14:24:54 -05:00 |
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Yehowshua Immanuel
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003a1c8545
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works even better now
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2025-02-19 18:28:08 -05:00 |
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Yehowshua Immanuel
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f9248057f9
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getting closer...
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2025-02-19 09:06:40 -05:00 |
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Yehowshua Immanuel
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32932f4816
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added basic decoding
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2025-02-19 01:21:02 -05:00 |
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Yehowshua Immanuel
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ef58d5b07e
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first commit
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2025-02-12 23:54:15 -05:00 |
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