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RiscV-Formal/hs
2025-03-07 22:04:40 -05:00
..
Peripherals Forgot to replace $ operator in Uart.hs 2025-03-06 08:44:28 -05:00
Bus.hs now fetching from ram correctly as ram is 32 bit word not byte indexed 2025-03-07 21:41:46 -05:00
BusTypes.hs Replacing $ operator with more readable |> operator 2025-03-06 08:41:00 -05:00
Cpu.hs clean up warnings a bit 2025-03-04 23:54:30 -05:00
Decode.hs still compiling after refactoring field types 2025-03-07 20:31:41 -05:00
DecodeTypes.hs still compiling after refactoring field types 2025-03-07 20:31:41 -05:00
Exceptions.hs created Decode result 2025-03-05 09:04:54 -05:00
Execute.hs working on adding read stage 2025-03-07 12:09:08 -05:00
Fetch.hs Replacing $ operator with more readable |> operator 2025-03-06 08:41:00 -05:00
Read.hs still compiling after refactoring field types 2025-03-07 20:31:41 -05:00
RegFiles.hs still compiling after refactoring field types 2025-03-07 20:31:41 -05:00
Simulation.hs reduce debug in sim and add PREFIX to makefile 2025-03-07 22:04:40 -05:00
Types.hs still compiling after refactoring field types 2025-03-07 20:31:41 -05:00
Util.hs Replacing $ operator with more readable |> operator 2025-03-06 08:41:00 -05:00