RiscV-Formal/hs
2025-03-13 14:31:38 -04:00
..
Peripherals Forgot to replace $ operator in Uart.hs 2025-03-06 08:44:28 -05:00
Bus.hs added needed context and getting ready to implement execute 2025-03-10 22:26:38 -04:00
BusTypes.hs added needed context and getting ready to implement execute 2025-03-10 22:26:38 -04:00
Cpu.hs clean up warnings a bit 2025-03-04 23:54:30 -05:00
Decode.hs added needed context and getting ready to implement execute 2025-03-10 22:26:38 -04:00
DecodeTypes.hs still compiling after refactoring field types 2025-03-07 20:31:41 -05:00
Exceptions.hs added needed context and getting ready to implement execute 2025-03-10 22:26:38 -04:00
Execute.hs fixed execution of R type instructions 2025-03-13 14:31:38 -04:00
Fetch.hs added needed context and getting ready to implement execute 2025-03-10 22:26:38 -04:00
Read.hs added needed context and getting ready to implement execute 2025-03-10 22:26:38 -04:00
RegFiles.hs read seemingly complete 2025-03-10 17:46:06 -04:00
Simulation.hs read seemingly complete 2025-03-10 17:46:06 -04:00
Types.hs still compiling after refactoring field types 2025-03-07 20:31:41 -05:00
Util.hs Replacing $ operator with more readable |> operator 2025-03-06 08:41:00 -05:00