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RiscV-Formal/hs
2025-03-07 18:41:55 -05:00
..
Peripherals Forgot to replace $ operator in Uart.hs 2025-03-06 08:44:28 -05:00
Bus.hs Replacing $ operator with more readable |> operator 2025-03-06 08:41:00 -05:00
BusTypes.hs Replacing $ operator with more readable |> operator 2025-03-06 08:41:00 -05:00
Cpu.hs clean up warnings a bit 2025-03-04 23:54:30 -05:00
Decode.hs working on adding read stage 2025-03-07 12:09:08 -05:00
DecodeTypes.hs created Decode result 2025-03-05 09:04:54 -05:00
Exceptions.hs created Decode result 2025-03-05 09:04:54 -05:00
Execute.hs working on adding read stage 2025-03-07 12:09:08 -05:00
Fetch.hs Replacing $ operator with more readable |> operator 2025-03-06 08:41:00 -05:00
Read.hs stopping point before re-factoring decoder types 2025-03-07 18:41:55 -05:00
RegFiles.hs Replacing $ operator with more readable |> operator 2025-03-06 08:41:00 -05:00
Simulation.hs Replacing $ operator with more readable |> operator 2025-03-06 08:41:00 -05:00
Types.hs hopefully progressing to a more scalable bus architecture 2025-02-25 14:24:54 -05:00
Util.hs Replacing $ operator with more readable |> operator 2025-03-06 08:41:00 -05:00