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• 39780a1ac2 Add prep_for_llm.sh main Yehowshua 2025-03-14 16:40:46 +0000
• 966fd30fa2 Merge pull request 'Add flake' (#4) from Artturin/RiscV-Formal:addnix into main Yehowshua 2025-03-14 15:55:41 +0000
• 8037eeba19 flake.nix: Remove cross glibc Artturin 2025-03-14 01:43:26 +0200
• 0960ceb53a rv_tests/hello_world: Rename PREFIX var to CROSS_PREFIX and make it configurable Artturin 2025-03-14 01:09:02 +0200
• ac8a2ea238 flake.nix: Comments Artturin 2025-03-14 00:43:24 +0200
• 56a80fe749 Riscv config Artturin 2025-03-14 00:17:51 +0200
• 2b9895f1cc Use newer ghc Artturin 2025-02-22 22:29:46 +0200
• c75ad4fa70 Remove stack.yaml Artturin 2025-02-22 22:15:33 +0200
• c82dfbe2a7 hello_world: Fix stat with coreutils(linux) Artturin 2025-02-22 21:44:28 +0200
• 3c14139753 Rename rv_formal.cabal to rvFormal Artturin 2025-02-21 23:13:45 +0200
• fec992cf2a Add flake Artturin 2025-02-22 22:13:14 +0200
• ad34d49f3d Fix shell.nix Artturin 2025-02-21 17:04:56 +0200
• a76d6e24ec correct behavior of R type in execute Yehowshua Immanuel 2025-03-13 16:26:03 -0400
• 4428f7f196 fixed execution of R type instructions Yehowshua Immanuel 2025-03-13 14:31:38 -0400
• 7066df0936 Grok mostly wrote execute - will test later... Yehowshua Immanuel 2025-03-10 23:00:23 -0400
• 69f5cdee6a added needed context and getting ready to implement execute Yehowshua Immanuel 2025-03-10 22:26:38 -0400
• b95b2b962a read seemingly complete Yehowshua Immanuel 2025-03-10 17:46:06 -0400
• ad751a5039 read is getting there... Yehowshua Immanuel 2025-03-10 17:22:51 -0400
• 171fcece98 reduce debug in sim and add PREFIX to makefile Yehowshua Immanuel 2025-03-07 22:04:40 -0500
• 63a73d3f71 now fetching from ram correctly as ram is 32 bit word not byte indexed Yehowshua Immanuel 2025-03-07 21:41:46 -0500
• 3f50fe32f8 still compiling after refactoring field types Yehowshua Immanuel 2025-03-07 20:31:41 -0500
• 73d5e1204c stopping point before re-factoring decoder types Yehowshua Immanuel 2025-03-07 18:41:55 -0500
• 6b81cd28ee working on adding read stage Yehowshua Immanuel 2025-03-07 12:09:08 -0500
• 4cc8c8d430 Forgot to replace $ operator in Uart.hs Yehowshua Immanuel 2025-03-06 08:44:28 -0500
• 0792bf3c7d Replacing $ operator with more readable |> operator Yehowshua Immanuel 2025-03-06 08:41:00 -0500
• 2b1c486c17 created Decode result Yehowshua Immanuel 2025-03-05 09:04:54 -0500
• a6c435791a improve instructions to simulate in README Yehowshua Immanuel 2025-03-05 00:10:56 -0500
• 7f7ba49ee1 prune more warnings and re-org Decode files a bit Yehowshua Immanuel 2025-03-05 00:09:04 -0500
• 67b44dedc0 clean up warnings a bit Yehowshua Immanuel 2025-03-04 23:54:30 -0500
• 30650b870c replace/update relevant fetch types and functions Yehowshua Immanuel 2025-03-04 23:43:35 -0500
• eb79210863 now using bus and new FetchResult type Yehowshua Immanuel 2025-03-04 23:37:33 -0500
• 4729d79b23 refactoring towards types that can handle exceptions between stages Yehowshua Immanuel 2025-03-04 23:05:52 -0500
• d7d698a28c save progress before switching to new bus architecture Yehowshua Immanuel 2025-03-04 08:12:59 -0500
• 88ec010f98 initial support for exceptions Yehowshua Immanuel 2025-03-02 23:12:02 -0500
• 5552ad3d4a bus architecture re-built I think Yehowshua Immanuel 2025-02-26 13:05:02 -0500
• c8b192cade prep for notable re-org Yehowshua Immanuel 2025-02-26 02:24:23 -0500
• 024115e389 Uart now has correct write implementation presumably Yehowshua Immanuel 2025-02-26 01:51:33 -0500
• 8d5cd862ab more progress on UART read Yehowshua Immanuel 2025-02-25 23:47:00 -0500
• 7265728932 read getting closer to being done Yehowshua Immanuel 2025-02-25 19:09:37 -0500
• 1f9bd2f015 hopefully progressing to a more scalable bus architecture Yehowshua Immanuel 2025-02-25 14:24:54 -0500
• 003a1c8545 works even better now Yehowshua Immanuel 2025-02-19 18:28:08 -0500
• f9248057f9 getting closer... Yehowshua Immanuel 2025-02-19 09:06:40 -0500
• 32932f4816 added basic decoding Yehowshua Immanuel 2025-02-19 01:21:02 -0500
• ef58d5b07e first commit Yehowshua Immanuel 2025-02-12 23:54:15 -0500