ReferenceProjects/riscv-bluespec-classic
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  • 51b96c9ea7 simplify C BSV Bindings wrappers main Yehowshua Immanuel 2025-04-22 11:59:53 -0400
  • 1b62021029 more work on uart server now with diagram Yehowshua Immanuel 2025-04-21 08:58:55 -0400
  • 842c19d441 make server map, normalize uart interfaces Yehowshua Immanuel 2025-04-20 18:06:17 -0400
  • 7290af88fb scaffolding for new uart interface in place Yehowshua Immanuel 2025-04-20 15:22:14 -0400
  • 89664a01f6 reduce noise in tag engine unit test as well as make results apparent Yehowshua Immanuel 2025-04-19 22:04:38 -0400
  • 2d9bc945c5 improve simulation egornomics a bit Yehowshua Immanuel 2025-04-19 21:51:30 -0400
  • f2a464b090 Merge pull request 'flake: Add missing input' (#18) from Artturin/riscv-bluespec-classic:fix-compat into main Yehowshua 2025-04-20 00:48:04 +0000
  • 9d897fccdc flake: Add missing input Artturin 2025-04-19 13:53:20 +0300
  • 44324eb803 need to start re-thinking structure of uart etc Yehowshua Immanuel 2025-04-18 19:42:03 -0400
  • d03cceb283 Merge pull request 'Add flake' (#7) from Artturin/riscv-bluespec-classic:addflake into main Yehowshua 2025-04-18 19:35:18 +0000
  • 7bc43946a9 Add compat files for non flakes users Artturin 2025-04-18 19:01:25 +0300
  • b89090f3ce flake.lock: Update Artturin 2025-04-18 18:59:23 +0300
  • c02e7b0de6 flake: Install the same file that fpga-starter-project-uart installed Artturin 2025-04-03 22:27:27 +0300
  • 7471c0188a Make make fpga work Artturin 2025-04-02 03:10:29 +0300
  • 1622e3ab6b Remove all trailing spaces Artturin 2025-04-02 03:04:44 +0300
  • 0dd4b60b70 Add initial flake Artturin 2025-04-02 02:59:21 +0300
  • d552934b95 Fixed grant bug Yehowshua Immanuel 2025-04-17 22:47:24 -0400
  • a58c908763 refactored server functions as well Yehowshua Immanuel 2025-04-16 22:47:50 -0400
  • 2fee6a3bd8 refactored client rules Yehowshua Immanuel 2025-04-16 22:34:52 -0400
  • 1557cf9cc9 working towards re-factoring into functions Yehowshua Immanuel 2025-04-16 22:10:49 -0400
  • 7d470fbed0 Merge pull request 'implement_Bus_alt1' (#16) from implement_Bus_alt1 into main Yehowshua 2025-04-16 22:00:14 +0000
  • ece1f86574 in theory bus is now complete Yehowshua Immanuel 2025-04-16 17:58:29 -0400
  • c28425f10c first attempt at server rule, also implemented consumeRequest of the server part of the Bus interface Yehowshua Immanuel 2025-04-16 16:55:45 -0400
  • a58c836981 worked on client arbiter but need to consider if starving is possible when multiple client arbiters grant access to the same server Yehowshua Immanuel 2025-04-15 18:21:42 -0400
  • f3acae0c1c potential scaffolding for new approach Yehowshua Immanuel 2025-04-15 14:15:49 -0400
  • 180eeeefbe we may not need dispatch by client Yehowshua Immanuel 2025-04-15 13:50:50 -0400
  • cd3d728083 some prep work to towards having a server accept a request Yehowshua Immanuel 2025-04-14 14:33:13 -0400
  • 373d170c3f notable progress WRT client requests invoking arbiter request Yehowshua Immanuel 2025-04-13 22:40:59 -0400
  • 98f2f5cdfd having trouble with type constraints around clientIdx Yehowshua Immanuel 2025-04-11 20:35:26 -0400
  • 813f543b42 request server from client rule in client issue Yehowshua Immanuel 2025-04-11 14:26:40 -0400
  • 628319709e stopping point Yehowshua Immanuel 2025-04-11 12:36:43 -0400
  • 45191a2abd WIP : client request should handle unmapped case Yehowshua Immanuel 2025-04-11 07:54:47 -0400
  • cffbadd1cc incomplete but need to come to stopping point Yehowshua Immanuel 2025-04-10 21:42:15 -0400
  • 5efef8b19c quieter builds, more type uniformity, full compiles Yehowshua Immanuel 2025-04-10 20:46:53 -0400
  • 548a2f26bd don't commit bkp files Yehowshua Immanuel 2025-04-10 11:01:41 -0400
  • 71fbb7d2e5 add bus diagram and further work on Bus Yehowshua Immanuel 2025-04-10 10:59:52 -0400
  • c9356eecfd client methods presumably finished Yehowshua Immanuel 2025-04-10 01:27:33 -0400
  • 979adf3660 preliminary work on client methods and some type repair Yehowshua Immanuel 2025-04-10 00:36:29 -0400
  • ca02c88be3 stubbed out mkBus for now - awaits full implementation Yehowshua Immanuel 2025-04-09 22:31:26 -0400
  • 076d3aed43 shoudl probably rethink approach... Yehowshua Immanuel 2025-04-09 20:58:13 -0400
  • b4c7537a85 things still typecheck Yehowshua Immanuel 2025-04-09 01:08:42 -0400
  • 989c4e9616 Bus types typecheck!!! Yehowshua Immanuel 2025-04-08 23:36:54 -0400
  • fe2fa21fcc skeletons of Bus module slowly forming Yehowshua Immanuel 2025-04-08 23:04:30 -0400
  • b326ac894e Add LICENSE Yehowshua 2025-04-08 23:36:08 +0000
  • da761f6e4e Type system progress on bus design Yehowshua Immanuel 2025-04-08 13:05:34 -0400
  • 2d5cf48c54 Merge pull request 'Tag Engine Now Finished it seems' (#10) from tag_engine_version_3 into main Yehowshua 2025-04-08 01:32:39 +0000
  • e415d981f9 add some comments Yehowshua Immanuel 2025-04-04 15:31:46 -0400
  • 020bc5b646 notable refactor with grok Yehowshua Immanuel 2025-04-04 15:27:25 -0400
  • ca59e6eaec handled tag engine edge case Yehowshua Immanuel 2025-04-04 15:09:56 -0400
  • 271148e538 better names in TagEngine Yehowshua Immanuel 2025-04-03 09:15:53 -0400
  • d1e3358197 now using wire instead of FIFO Yehowshua Immanuel 2025-04-02 03:03:39 -0400
  • e055b1bbdf reduced latency Yehowshua Immanuel 2025-04-02 02:59:49 -0400
  • d436209f54 seemingly reasonable stopping point Yehowshua Immanuel 2025-04-02 02:09:41 -0400
  • 6247ae3b70 clean unused experiments Yehowshua Immanuel 2025-03-25 08:48:43 -0400
  • 0452f44fbd alternate approach not so successful repair_tag_engine_alternate Yehowshua Immanuel 2025-03-25 08:35:17 -0400
  • e89254ebef eliminate warnings Yehowshua Immanuel 2025-03-25 08:03:04 -0400
  • ed8e0b8337 tag engine now allows from simultaneous retire and request - but had to use unsafe Yehowshua Immanuel 2025-03-25 01:15:49 -0400
  • 5588fafebd refactor into standalone TagEngineTester Yehowshua Immanuel 2025-03-24 23:23:39 -0400
  • 6e3b3e9178 Preliminary cleaning before repairing TagEngine Yehowshua Immanuel 2025-03-24 22:46:42 -0400
  • 7c32974f7b update readme Yehowshua Immanuel 2025-03-24 08:24:06 -0400
  • 76e542ff36 tested and seems to be working Yehowshua Immanuel 2025-03-23 18:45:32 -0400
  • 35fc49382d reverting as it seems we really cant condition rules on arguments safely Yehowshua Immanuel 2025-03-23 18:30:56 -0400
  • 996febbff5 change interface Yehowshua Immanuel 2025-03-23 17:58:56 -0400
  • e6b002f70e added informative comment Yehowshua Immanuel 2025-03-23 08:12:40 -0400
  • c5ad62aaed Greatly simpliflied tag engine to use stack implementation. Having trouble guarding on interface argument... Yehowshua Immanuel 2025-03-23 08:12:24 -0400
  • 8e27ca877f beginning of a linked list in hardware Yehowshua Immanuel 2025-03-20 17:00:15 -0400
  • 7ad812d3da refactor a bit Yehowshua Immanuel 2025-03-20 13:27:01 -0400
  • 5f2d9456ae Tag engine building Yehowshua Immanuel 2025-03-20 06:28:55 -0400
  • ac48f5a4ad unable to display fshow for tagVec Yehowshua Immanuel 2025-03-20 00:10:00 -0400
  • 6359ab833d tag types and moodularity improving Yehowshua Immanuel 2025-03-19 23:08:58 -0400
  • 4422947f9a TageEngine now typechecks Yehowshua Immanuel 2025-03-19 22:10:14 -0400
  • a3afd66715 begun work on tag engine Yehowshua Immanuel 2025-03-17 12:04:42 -0400
  • 550b3731b4 still workikng on Bus types Yehowshua Immanuel 2025-03-17 09:16:22 -0400
  • 21a3ee7f7a initial support for Bus types Yehowshua Immanuel 2025-03-14 19:46:08 -0400
  • 66464daf0c Update README.md Yehowshua 2025-03-14 16:30:45 +0000
  • 258534808c correct README indentation Yehowshua Immanuel 2024-05-19 22:21:33 -0400
  • 4c8298f2a1 update README and remove BRAM experiments Yehowshua Immanuel 2024-05-19 22:20:53 -0400
  • cf68a5e683 converted to bluespec haskell Yehowshua Immanuel 2024-05-19 22:16:33 -0400
  • 72788b8436 using bluespec classic for BRAM testbench Yehowshua Immanuel 2024-05-19 01:14:17 -0400
  • 10ed5b8751 ready for demo Yehowshua Immanuel 2024-03-20 03:30:28 -0400
  • 83f78d1c3d add comment Yehowshua Immanuel 2024-03-20 02:52:44 -0400
  • 423ea6142e improve some indentation in src/Top.bsv Yehowshua Immanuel 2024-03-20 02:49:08 -0400
  • 95631e77b8 update README with instructions for simulating main core Yehowshua Immanuel 2024-03-20 02:48:49 -0400
  • 338cdac474 Remove .DS_Store files Yehowshua Immanuel 2024-03-20 02:39:13 -0400
  • aad8289d4e now with info on how to simulate experimental BRAM Yehowshua Immanuel 2024-03-20 02:37:24 -0400
  • e44f6b083b it's been a while Yehowshua Immanuel 2024-03-20 02:25:31 -0400
  • 9f90b00b25 wow - loopback in sim actually worksgit status Yehowshua Immanuel 2023-09-28 06:57:38 -0400
  • ad1bdfc8b1 fix typos and improve spaces Yehowshua Immanuel 2023-09-26 00:41:21 -0400
  • c3c2cd53e1 working towards sim uart-like device support Yehowshua Immanuel 2023-09-26 00:40:04 -0400
  • dc11528567 sim now working Yehowshua Immanuel 2023-09-25 20:21:23 -0400
  • 3be337c4d6 restore hopefully all remaining pragmas Yehowshua Immanuel 2023-09-25 03:44:40 -0400
  • e0b5d55387 restore missing pragma Yehowshua Immanuel 2023-09-25 03:37:13 -0400
  • 257507e3fa conversion complete Yehowshua Immanuel 2023-09-25 03:34:21 -0400
  • 1209f6a700 now converted clock divider Yehowshua Immanuel 2023-09-25 02:45:27 -0400
  • b1c14f5aba first commit Yehowshua Immanuel 2023-09-23 02:08:37 -0400