make server map, normalize uart interfaces

This commit is contained in:
Yehowshua Immanuel 2025-04-20 18:06:17 -04:00
parent 7290af88fb
commit 842c19d441
3 changed files with 38 additions and 2 deletions

35
bs/ServerMap.bs Normal file
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@ -0,0 +1,35 @@
package ServerMap(
ramServerStart,
ramServerEnd,
uartServerStart,
uartServerEnd,
serverMap
) where
import Types
import BusTypes
bytesInRam :: Types.Addr
bytesInRam = 1024
-- number of servers currently supported by this bus map
type NumServers = 2
ramServerStart :: Types.Addr
ramServerStart = 0x80000000
ramServerEnd :: Types.Addr
ramServerEnd = ramServerStart + (bytesInRam - 1)
uartServerStart :: Types.Addr
uartServerStart = 0x10000000
uartServerEnd :: Types.Addr
uartServerEnd = uartServerStart + 7
-- be careful when hooking up the servers that
-- the uart is attached to index 0 whilst the ram
-- is attached to index 1
serverMap :: Types.Addr -> Maybe (MkServerIdx 2)
serverMap addr =
if addr >= ramServerStart && addr <= ramServerEnd then Just 1
else if addr >= uartServerStart && addr <= uartServerEnd then Just 0
else Nothing

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@ -13,6 +13,7 @@ import ActionSeq
import Vector
import BusTypes
import Uart
import ServerMap
import TagEngineTester

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@ -22,5 +22,5 @@ mkUartPhy dedicatedServerInterface = do
return |>
interface UartPhy
bitOut = 1
bitIn bitVal = do
action {}
bitIn bitVal = do
deserializer.putBitIn bitVal