make server map, normalize uart interfaces
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parent
7290af88fb
commit
842c19d441
35
bs/ServerMap.bs
Normal file
35
bs/ServerMap.bs
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@ -0,0 +1,35 @@
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package ServerMap(
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ramServerStart,
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ramServerEnd,
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uartServerStart,
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uartServerEnd,
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serverMap
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) where
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import Types
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import BusTypes
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bytesInRam :: Types.Addr
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bytesInRam = 1024
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-- number of servers currently supported by this bus map
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type NumServers = 2
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ramServerStart :: Types.Addr
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ramServerStart = 0x80000000
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ramServerEnd :: Types.Addr
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ramServerEnd = ramServerStart + (bytesInRam - 1)
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uartServerStart :: Types.Addr
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uartServerStart = 0x10000000
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uartServerEnd :: Types.Addr
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uartServerEnd = uartServerStart + 7
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-- be careful when hooking up the servers that
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-- the uart is attached to index 0 whilst the ram
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-- is attached to index 1
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serverMap :: Types.Addr -> Maybe (MkServerIdx 2)
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serverMap addr =
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if addr >= ramServerStart && addr <= ramServerEnd then Just 1
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else if addr >= uartServerStart && addr <= uartServerEnd then Just 0
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else Nothing
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@ -13,6 +13,7 @@ import ActionSeq
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import Vector
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import BusTypes
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import Uart
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import ServerMap
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import TagEngineTester
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@ -22,5 +22,5 @@ mkUartPhy dedicatedServerInterface = do
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return |>
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interface UartPhy
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bitOut = 1
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bitIn bitVal = do
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action {}
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bitIn bitVal = do
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deserializer.putBitIn bitVal
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