ReferenceProjects/riscv-bluespec-classic
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Yehowshua Immanuel 2024-03-20 02:52:44 -04:00
parent 423ea6142e
commit 83f78d1c3d
1 changed files with 4 additions and 2 deletions
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src/Top.bsv
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@ -69,8 +69,8 @@ endmodule
module mkSim(Empty);
BRAM_Configure cfg = defaultValue;
// Define a 3-bit register named count
Reg#(UInt#(3)) count <- mkReg(0);
// Define a 3-bit register named count
Reg#(UInt#(3)) count <- mkReg(0);
Reg#(Bool) init_C_functions <- mkReg(False);
Core#(FCLK) core <- mkCore();
@ -80,6 +80,8 @@ module mkSim(Empty);
init_C_functions <= True;
endrule
// implicit true - should always fire - effective making
// a loopback
rule core_char_device_o;
write_char_to_terminal(core.get_char);
endrule