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Yehowshua 2025-03-14 16:30:45 +00:00
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@ -60,7 +60,7 @@ TOPMODULE=mkTop make v_compile
- [ ] debug UART accuracy
- clk divider should be frequency matched
- [ ] move to JoyOfHardware
- [ ] port in [PPC_Formal](https://github.com/JoyOfHardware/PPC_Formal)
- [ ] port in [RiscV-Formal](https://git.joyofhardware.com/Yehowshua/RiscV-Formal)
- [ ] create I and D caches
- [ ] try to optimize decoder