conversion complete

README.md

@@ -35,4 +35,7 @@ TOPMODULE=mkTop make v_compile
 ```
 
 # TODO
- - [ ] debug UART accuracy
+ - [ ] debug UART accuracy
+
+# Notable Reference Files
+``/Users/yehowshuaimmanuel/git/bsc/testsuite/bsc.bsv_examples/cpu/FiveStageCPUQ3sol.bsv``

src/ClkDivider.bsv

@@ -21,7 +21,7 @@ module mkClkDivider#(Handle fileHandle)(ClkDivider#(hi));
     hPutStr(fileHandle, genModuleName);
 
     rule tick;
-        $display(counter);
+        // $display(counter);
         counter <= (counter == hi_value) ? 0 : counter + 1;
     endrule
 

src/Deserializer.bsv

@@ -0,0 +1,52 @@
+package Deserializer;
+export mkDeserialize;
+
+export IDeserializer(..);
+
+export State(..);
+
+import ClkDivider::*;
+
+import State::*;
+
+interface IDeserializer#(numeric type clkFreq, numeric type baudRate);
+    method Bit#(8) get();
+    method Action putBitIn(Bit#(1) bitIn);
+endinterface
+
+module mkDeserialize#(Handle fileHandle)(IDeserializer#(clkFreq, baudRate));
+    Wire#(Bit#(1)) ftdiRxIn <- mkBypassWire;
+    Reg#(Bit#(8)) shiftReg <- mkReg(0);
+    Reg#(State) ftdiState <- mkReg(IDLE);
+    
+    ClkDivider#(TDiv#(clkFreq, baudRate)) clkDivider <- mkClkDivider(fileHandle);
+
+    (* fire_when_enabled *)
+    rule idle (ftdiState == IDLE && ftdiRxIn == 0);
+        clkDivider.reset();
+        ftdiState <= ftdiStateNext(ftdiState);
+    endrule
+
+    (* fire_when_enabled *)
+    rule not_idle (ftdiState != IDLE && clkDivider.isAdvancing());
+        ftdiState <= ftdiStateNext(ftdiState);
+    endrule
+
+    (* fire_when_enabled *)
+    rule sampling (
+          ftdiState matches (tagged DATA .n) &&& 
+          clkDivider.isHalfCycle()
+          );
+        shiftReg <= {ftdiRxIn, shiftReg[7:1]};
+    endrule
+
+    method Bit#(8) get() if (ftdiState == STOP && clkDivider.isAdvancing());
+        return shiftReg;
+    endmethod
+
+    method Action putBitIn(Bit#(1) bitIn);
+        ftdiRxIn <= bitIn;
+    endmethod
+endmodule
+
+endpackage

src/Serializer.bsv

@@ -0,0 +1,51 @@
+package Serializer;
+
+import ClkDivider::*;
+import State::*;
+
+export mkSerialize;
+export ISerializer(..);
+export State(..);
+
+function Bit#(1) serialize(State state, Bit#(8) dataReg);
+    case (state) matches
+        tagged START    : return 1'b0;
+        tagged DATA .n   : return dataReg[n];
+        default  : return 1'b1;
+    endcase
+endfunction
+
+interface ISerializer#(numeric type clkFreq, numeric type baudRate);
+    method Action putBit8(Bit#(8) bit8Val);
+    method Bit#(1) bitLineOut();
+endinterface
+
+module mkSerialize#(Handle fileHandle)(ISerializer#(clkFreq, baudRate));
+    Wire#(Bit#(1)) ftdiTxOut <- mkBypassWire();
+    Reg#(Bit#(8)) dataReg <- mkReg(0);
+    Reg#(State) ftdiState <- mkReg(IDLE);
+
+    ClkDivider#(TDiv#(clkFreq, baudRate)) clkDivider <- mkClkDivider(fileHandle);
+
+    (* fire_when_enabled *)
+    rule advanceUartState (ftdiState != IDLE && clkDivider.isAdvancing());
+        ftdiState <= ftdiStateNext(ftdiState);
+    endrule
+
+    (* fire_when_enabled *)
+    rule bitLine (ftdiState != IDLE);
+        ftdiTxOut <= serialize(ftdiState, dataReg);
+    endrule
+
+    method Action putBit8(Bit#(8) bit8Val) if (ftdiState == IDLE);
+        clkDivider.reset();
+        dataReg <= bit8Val;
+        ftdiState <= ftdiStateNext(ftdiState);
+    endmethod
+
+    method Bit#(1) bitLineOut;
+        return ftdiTxOut;
+    endmethod
+endmodule
+
+endpackage