52 lines
1.3 KiB
Plaintext
52 lines
1.3 KiB
Plaintext
package Deserializer;
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export mkDeserialize;
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export IDeserializer(..);
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export State(..);
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import ClkDivider::*;
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import State::*;
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interface IDeserializer#(numeric type clkFreq, numeric type baudRate);
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method Bit#(8) get();
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method Action putBitIn(Bit#(1) bitIn);
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endinterface
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module mkDeserialize#(Handle fileHandle)(IDeserializer#(clkFreq, baudRate));
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Wire#(Bit#(1)) ftdiRxIn <- mkBypassWire;
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Reg#(Bit#(8)) shiftReg <- mkReg(0);
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Reg#(State) ftdiState <- mkReg(IDLE);
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ClkDivider#(TDiv#(clkFreq, baudRate)) clkDivider <- mkClkDivider(fileHandle);
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(* fire_when_enabled *)
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rule idle (ftdiState == IDLE && ftdiRxIn == 0);
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clkDivider.reset();
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ftdiState <= ftdiStateNext(ftdiState);
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endrule
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(* fire_when_enabled *)
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rule not_idle (ftdiState != IDLE && clkDivider.isAdvancing());
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ftdiState <= ftdiStateNext(ftdiState);
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endrule
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(* fire_when_enabled *)
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rule sampling (
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ftdiState matches (tagged DATA .n) &&&
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clkDivider.isHalfCycle()
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);
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shiftReg <= {ftdiRxIn, shiftReg[7:1]};
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endrule
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method Bit#(8) get() if (ftdiState == STOP && clkDivider.isAdvancing());
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return shiftReg;
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endmethod
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method Action putBitIn(Bit#(1) bitIn);
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ftdiRxIn <= bitIn;
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endmethod
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endmodule
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endpackage |