update README and remove BRAM experiments

README.md

@@ -59,6 +59,10 @@ TOPMODULE=mkTop make v_compile
 # TODO
  - [ ] debug UART accuracy
        - clk divider should be frequency matched
+ - [ ] move to JoyOfHardware
+ - [ ] port in [PPC_Formal](https://github.com/JoyOfHardware/PPC_Formal)
+       - [ ] create I and D caches
+       - [ ] try to optimize decoder
 
 # Notable Reference Files
 ``/Users/yehowshuaimmanuel/git/bsc/testsuite/bsc.bsv_examples/cpu/FiveStageCPUQ3sol.bsv``

experiments/bram/README.md

@@ -1,23 +0,0 @@
-# About
-
-Trying to get a feel for what might constitute a good flow when
-needing to inspect simulated memories in Bluespec.
-
-Here, we simulate a small BRAM and try to print out some of its 
-values in TCL.
-
-# Compiling and Simulating 
-
-## Without TCL
-
-```bash
-bsc -sim -u -g mkTestbench Testbench.bs; bsc -sim -e mkTestbench -o simBRAM;
-./simBRAM -V
-```
-
-## With TCL
-
-```bash
-bsc -sim -u -g mkTestbench Testbench.bs; bsc -sim -e mkTestbench -o simBRAM;
-bluetcl sim_inspect.tcl
-```

experiments/bram/Testbench.bs

@@ -1,58 +0,0 @@
--- bsc -sim -u -g mkTestbench Testbench.bs; bsc -sim -e mkTestbench -o simBRAM;
-package Testbench where
-
-import BRAM
-import StmtFSM;
-import Clocks;
-import ActionSeq;
-
-makeRequest :: Bool -> Bit 8 -> Bit 8 -> BRAMRequest (Bit 8) (Bit 8);
-makeRequest write addr dat = 
-  BRAMRequest { 
-    write = write;
-    responseOnWrite = False; 
-    address = addr; 
-    datain = dat; 
-    }
-
-{-# properties mkTestbench = { verilog } #-}
-mkTestbench :: Module Empty
-mkTestbench = do
-  let cfg :: BRAM_Configure = defaultValue {
-    allowWriteResponseBypass = False;
-    loadFormat = Hex "bram2.txt";
-    };
-
-  count :: Reg (UInt 3) <- mkReg 0;
-  dut1 :: BRAM1Port (Bit 8) (Bit 8) <- mkBRAM1Server cfg;
-
-  done :: Reg Bool
-  done <- mkReg False
-
-  s :: ActionSeq
-  s <- actionSeq 
-    $  do
-         $display "count = %d" count
-         dut1.portA.request.put $ makeRequest False 0 0
-    |> do
-         $display "count = %d" count
-         $display "dut1read[0] = %x" dut1.portA.response.get
-         dut1.portA.request.put $ makeRequest False 1 0
-    |> do
-         $display "count = %d" count
-         $display "dut1read[1] = %x" dut1.portA.response.get
-         dut1.portA.request.put $ makeRequest False 2 0
-    |> do
-         $display "count = %d" count
-         $display "dut1read[2] = %x" dut1.portA.response.get
-    |> do
-         $finish
-
-  addRules $
-    rules
-      "counting" : when True ==>
-        do
-          count := 3
-          s.start
-
-  return $ interface Empty

experiments/bram/bram2.txt

@@ -1,4 +0,0 @@
-fe
-ed
-f0
-0d

experiments/bram/sim_inspect.tcl

@@ -1,14 +0,0 @@
-# bluetcl sim_inspect.tcl
-namespace import ::Bluetcl::*
-package require Bluesim
-
-sim load simBRAM.so mkTestbench
-set count_hdl [sim lookup count]
-set bram [sim lookup dut1_memory]
-
-sim step
-sim step
-sim step
-
-puts "Value of count: [sim get $count_hdl]"
-puts "Value of bram\[0:3\]: [sim getrange $bram 0 3]"