58 lines
1.4 KiB
Haskell
58 lines
1.4 KiB
Haskell
-- bsc -sim -u -g mkTestbench Testbench.bs; bsc -sim -e mkTestbench -o simBRAM;
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package Testbench where
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import BRAM
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import StmtFSM;
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import Clocks;
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import ActionSeq;
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makeRequest :: Bool -> Bit 8 -> Bit 8 -> BRAMRequest (Bit 8) (Bit 8);
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makeRequest write addr dat =
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BRAMRequest {
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write = write;
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responseOnWrite = False;
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address = addr;
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datain = dat;
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}
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{-# properties mkTestbench = { verilog } #-}
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mkTestbench :: Module Empty
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mkTestbench = do
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let cfg :: BRAM_Configure = defaultValue {
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allowWriteResponseBypass = False;
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loadFormat = Hex "bram2.txt";
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};
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count :: Reg (UInt 3) <- mkReg 0;
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dut1 :: BRAM1Port (Bit 8) (Bit 8) <- mkBRAM1Server cfg;
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done :: Reg Bool
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done <- mkReg False
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s :: ActionSeq
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s <- actionSeq
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$ do
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$display "count = %d" count
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dut1.portA.request.put $ makeRequest False 0 0
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|> do
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$display "count = %d" count
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$display "dut1read[0] = %x" dut1.portA.response.get
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dut1.portA.request.put $ makeRequest False 1 0
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|> do
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$display "count = %d" count
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$display "dut1read[1] = %x" dut1.portA.response.get
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dut1.portA.request.put $ makeRequest False 2 0
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|> do
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$display "count = %d" count
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$display "dut1read[2] = %x" dut1.portA.response.get
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|> do
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$finish
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addRules $
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rules
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"counting" : when True ==>
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do
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count := 3
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s.start
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return $ interface Empty |