 Yehowshua Immanuel
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7c32974f7b
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update readme
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2025-03-24 08:24:06 -04:00 |
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Yehowshua Immanuel
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76e542ff36
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tested and seems to be working
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2025-03-23 18:45:32 -04:00 |
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Yehowshua Immanuel
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35fc49382d
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reverting as it seems we really cant condition rules on arguments safely
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2025-03-23 18:30:56 -04:00 |
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Yehowshua Immanuel
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996febbff5
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change interface
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2025-03-23 17:58:56 -04:00 |
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Yehowshua Immanuel
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e6b002f70e
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added informative comment
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2025-03-23 08:12:40 -04:00 |
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Yehowshua Immanuel
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c5ad62aaed
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Greatly simpliflied tag engine to use stack implementation. Having trouble guarding on interface argument...
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2025-03-23 08:12:24 -04:00 |
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Yehowshua Immanuel
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8e27ca877f
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beginning of a linked list in hardware
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2025-03-20 17:00:15 -04:00 |
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Yehowshua Immanuel
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7ad812d3da
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refactor a bit
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2025-03-20 13:27:01 -04:00 |
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Yehowshua Immanuel
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5f2d9456ae
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Tag engine building
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2025-03-20 06:28:55 -04:00 |
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Yehowshua Immanuel
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ac48f5a4ad
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unable to display fshow for tagVec
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2025-03-20 00:10:00 -04:00 |
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Yehowshua Immanuel
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6359ab833d
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tag types and moodularity improving
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2025-03-19 23:08:58 -04:00 |
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Yehowshua Immanuel
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4422947f9a
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TageEngine now typechecks
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2025-03-19 22:10:14 -04:00 |
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Yehowshua Immanuel
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a3afd66715
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begun work on tag engine
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2025-03-17 12:04:42 -04:00 |
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Yehowshua Immanuel
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550b3731b4
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still workikng on Bus types
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2025-03-17 09:16:22 -04:00 |
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Yehowshua Immanuel
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21a3ee7f7a
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initial support for Bus types
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2025-03-14 19:46:08 -04:00 |
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Yehowshua
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66464daf0c
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Update README.md
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2025-03-14 16:30:45 +00:00 |
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Yehowshua Immanuel
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258534808c
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correct README indentation
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2024-05-19 22:21:33 -04:00 |
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Yehowshua Immanuel
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4c8298f2a1
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update README and remove BRAM experiments
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2024-05-19 22:20:53 -04:00 |
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Yehowshua Immanuel
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cf68a5e683
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converted to bluespec haskell
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2024-05-19 22:16:33 -04:00 |
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Yehowshua Immanuel
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72788b8436
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using bluespec classic for BRAM testbench
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2024-05-19 01:14:17 -04:00 |
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Yehowshua Immanuel
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10ed5b8751
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ready for demo
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2024-03-20 03:30:28 -04:00 |
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Yehowshua Immanuel
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83f78d1c3d
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add comment
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2024-03-20 02:52:44 -04:00 |
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Yehowshua Immanuel
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423ea6142e
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improve some indentation in src/Top.bsv
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2024-03-20 02:49:08 -04:00 |
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Yehowshua Immanuel
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95631e77b8
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update README with instructions for simulating main core
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2024-03-20 02:48:49 -04:00 |
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Yehowshua Immanuel
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338cdac474
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Remove .DS_Store files
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2024-03-20 02:39:13 -04:00 |
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Yehowshua Immanuel
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aad8289d4e
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now with info on how to simulate experimental BRAM
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2024-03-20 02:37:24 -04:00 |
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Yehowshua Immanuel
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e44f6b083b
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it's been a while
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2024-03-20 02:25:31 -04:00 |
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Yehowshua Immanuel
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9f90b00b25
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wow - loopback in sim actually worksgit status
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2023-09-28 06:57:38 -04:00 |
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Yehowshua Immanuel
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ad1bdfc8b1
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fix typos and improve spaces
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2023-09-26 00:41:21 -04:00 |
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Yehowshua Immanuel
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c3c2cd53e1
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working towards sim uart-like device support
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2023-09-26 00:40:04 -04:00 |
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Yehowshua Immanuel
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dc11528567
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sim now working
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2023-09-25 20:21:23 -04:00 |
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Yehowshua Immanuel
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3be337c4d6
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restore hopefully all remaining pragmas
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2023-09-25 03:44:40 -04:00 |
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Yehowshua Immanuel
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e0b5d55387
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restore missing pragma
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2023-09-25 03:37:13 -04:00 |
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Yehowshua Immanuel
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257507e3fa
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conversion complete
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2023-09-25 03:34:21 -04:00 |
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Yehowshua Immanuel
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1209f6a700
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now converted clock divider
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2023-09-25 02:45:27 -04:00 |
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Yehowshua Immanuel
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b1c14f5aba
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first commit
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2023-09-23 02:08:37 -04:00 |
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