initial support for Bus types
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7
bs/Bus.bs
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7
bs/Bus.bs
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package Bus(a) where
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import Types
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import BusTypes
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a :: UInt 5
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a = 3
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33
bs/BusTypes.bs
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33
bs/BusTypes.bs
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@ -0,0 +1,33 @@
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package BusTypes(BusVal, TransactionSize) where
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import Types
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data BusError
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= UnMapped
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| UnAligned
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deriving (Bits, Eq, FShow)
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data TransactionSize
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= SizeByte
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| SizeHalfWord
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| SizeFullWord
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| SizeDoubleWord
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| SizeQuadWord
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deriving (Bits, Eq, FShow)
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data BusVal
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= BusByte Byte
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| BusHalfWord HalfWord
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| BusFullWord FullWord
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| BusDoubleWord DoubleWord
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| BusQuadWord QuadWord
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deriving (Bits, Eq, FShow)
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data ReadRequest = ReadRequest Addr TransactionSize
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deriving (Bits, Eq, FShow)
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data WriteRequest = WriteRequest Addr BusVal
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deriving (Bits, Eq, FShow)
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a :: UInt 5
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a = 3
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@ -5,6 +5,7 @@ import Core
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import Serializer
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import BRAM
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import CBindings
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import Bus
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type FCLK = 25000000
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type BAUD = 9600
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@ -24,7 +25,7 @@ mkTop = do
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persistLed :: Reg (Bit 8) <- mkReg 0
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messageM $ "Hallo!!" + (realToString 5)
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-- refactor such that the following rules are let-bound to
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-- refactor such that the following rules are let-bound to
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-- `attachIO` identifier
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addRules $
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rules
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@ -43,7 +44,7 @@ mkTop = do
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return $
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interface ITop
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ftdi_rxd = serializer.bitLineOut
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ftdi_txd bitIn =
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ftdi_txd bitIn =
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do
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deserializer.putBitIn bitIn
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led = persistLed
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@ -73,4 +74,4 @@ mkSim = do
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do
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restoreTerminal
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$display "GOT CTRL+C"
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$finish
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$finish
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15
bs/Types.bs
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15
bs/Types.bs
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@ -0,0 +1,15 @@
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package Types(
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Pc, Insn, Addr,
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Byte, HalfWord, FullWord, DoubleWord, QuadWord
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)
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where
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type Byte = UInt 8
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type HalfWord = UInt 16
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type FullWord = UInt 32
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type DoubleWord = UInt 64
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type QuadWord = UInt 128
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type Insn = FullWord
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type Pc = DoubleWord
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type Addr = DoubleWord
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