Yehowshua Immanuel
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69f5cdee6a
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added needed context and getting ready to implement execute
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2025-03-10 22:26:38 -04:00 |
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 Yehowshua Immanuel
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63a73d3f71
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now fetching from ram correctly as ram is 32 bit word not byte indexed
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2025-03-07 21:41:46 -05:00 |
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Yehowshua Immanuel
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0792bf3c7d
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Replacing $ operator with more readable |> operator
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2025-03-06 08:41:00 -05:00 |
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Yehowshua Immanuel
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67b44dedc0
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clean up warnings a bit
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2025-03-04 23:54:30 -05:00 |
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Yehowshua Immanuel
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88ec010f98
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initial support for exceptions
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2025-03-02 23:12:02 -05:00 |
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Yehowshua Immanuel
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5552ad3d4a
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bus architecture re-built I think
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2025-02-26 13:05:02 -05:00 |
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Yehowshua Immanuel
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c8b192cade
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prep for notable re-org
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2025-02-26 02:24:23 -05:00 |
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Yehowshua Immanuel
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024115e389
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Uart now has correct write implementation presumably
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2025-02-26 01:51:33 -05:00 |
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Yehowshua Immanuel
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8d5cd862ab
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more progress on UART read
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2025-02-25 23:47:00 -05:00 |
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Yehowshua Immanuel
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7265728932
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read getting closer to being done
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2025-02-25 19:09:37 -05:00 |
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Yehowshua Immanuel
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1f9bd2f015
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hopefully progressing to a more scalable bus architecture
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2025-02-25 14:24:54 -05:00 |
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