45 lines
1.5 KiB
Haskell
45 lines
1.5 KiB
Haskell
{-# OPTIONS_GHC -Wno-unrecognised-pragmas #-}
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module Bus() where
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import Clash.Prelude
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import Peripherals.Ram(Ram, RamLine, read, RamAddr)
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import Machine(Peripherals(..))
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import BusTypes(
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BusError(..),
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TransactionSize(..),
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Request(..),
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BusResponse(..),
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BusVal(..),
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ReadResponse(..),
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WriteResponse(..)
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)
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import Types(Addr,
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Byte, HalfWord, FullWord, DoubleWord, QuadWord)
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import Peripherals.Ram(read, bytesInRam)
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import Distribution.Types.UnitId (DefUnitId(unDefUnitId))
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alignCheck :: Addr -> TransactionSize -> Bool
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alignCheck addr SizeByte = True
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alignCheck addr SizeHalfWord = addr `mod` 2 == 0
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alignCheck addr SizeFullWord = addr `mod` 4 == 0
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alignCheck addr SizeDoubleWord = addr `mod` 8 == 0
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alignCheck addr SizeQuadWord = addr `mod` 16 == 0
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-- address space follows QEMU behavior for now
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(ramStart, ramEnd) = (0x80000000 :: Addr, ramStart + (bytesInRam - 1))
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(uartStart, uartEnd) = (0x10000000 :: Addr, uartStart + 7)
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-- reading/writing from/to UART is implemented as reading/writing
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-- from/to STDIO, so we need IO.
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read :: Request -> Peripherals -> IO ReadResponse
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read (Request addr size) peripherals
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| not (alignCheck addr size) = return $ ReadResponse $ Error UnAligned
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| (addr > ramStart) && (addr < ramEnd) =
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return $ ReadResponse $ Result $ Peripherals.Ram.read size ramAddr (ram peripherals)
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| otherwise = return $ ReadResponse $ Error UnMapped
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where
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ramAddrNoOffset = addr - ramStart
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ramAddr :: RamAddr
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ramAddr = resize ramAddrNoOffset
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