ReferenceProjects/riscv-bluespec-classic
Archived
1
0
Fork 0
Code Issues 13 Pull requests Projects Releases Packages Wiki Activity Actions

more work on uart server now with diagram

Browse source
This commit is contained in:
Yehowshua Immanuel 2025-04-21 08:58:55 -04:00
parent 842c19d441
commit 1b62021029
2 changed files with 128 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

10
bs/Uart/Uart.bs
View file

@ -6,8 +6,13 @@ package Uart(
import Serializer
import Deserializer
import BusTypes
import Types
import Util
import FIFO
import FIFOF
import SpecialFIFOs
-- Out is out from the FPGA and In is in to the FPGA
interface (UartPhy :: # -> # -> *) clkFreq baudRate =
bitOut :: Bit 1
@ -18,7 +23,10 @@ mkUartPhy :: (BusTypes.BusServer inFlightTransactions numClients)
mkUartPhy dedicatedServerInterface = do
fileHandle :: Handle <- openFile "mkUartPhy.log" WriteMode
deserializer :: Deserializer clkFreq baudRate <- mkDeserialize fileHandle
serializer :: Serializer clkFreq baudRate <- mkSerialize fileHandle
serializer :: Serializer clkFreq baudRate <- mkSerialize fileHandle
taggedResponseBuffer :: (FIFO (BusTypes.TaggedBusResponse inFlightTransactions)) <- mkFIFO
return |>
interface UartPhy
bitOut = 1