now parsing memory statements
This commit is contained in:
Yehowshua Immanuel
parent
cbbc7e73bd
commit
38fb13556f
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@ -3,6 +3,7 @@ module Main where
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import System.Environment (getArgs)
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import System.IO
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import Control.Exception (catch, IOException)
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import Text.Show.Pretty (ppShow)
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import Haskellator
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@ -19,7 +20,7 @@ main = do
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putStrLn "File Contents:"
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putStrLn contents
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[] -> putStrLn "cabal run Haskellator -- <file-path>"
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putStrLn $ show Haskellator.val
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putStrLn $ ppShow Haskellator.val
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-- Handle potential file reading errors
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handleReadError :: IOException -> IO String
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14
atoms.txt
14
atoms.txt
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@ -5,8 +5,8 @@
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- [x] <decimal-digit> ::= “0” | “1” | “2” | “3” | “4” | “5” | “6” | “7” | “8” | “9”
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- [x] <binary-digit> ::= “0” | “1” | “x” | “z” | “m” | “-“
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- [x] <integer> ::= “-“? <decimal-digit>+
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- [ ] <file> ::= <autoidx-stmt>? <module>*
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- [x] <autoidx-stmt> ::= “autoidx” <integer> <eol>
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- [ ] <file> ::= <autoidx-stmt>? <module>*
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- [ ] <module> ::= <attr-stmt>* <module-stmt> <module-body> <module-end-stmt>
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- [x] <module-stmt> ::= “module” <id> <eol>
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- [ ] <module-body> ::= (<param-stmt> | <wire> | <memory> | <cell> | <process> )*
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@ -14,12 +14,12 @@
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- [x] <constant> ::= <value> | <integer> | <string>
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- [x] <module-end-stmt> ::= “end” <eol>
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- [x] <attr-stmt> ::= “attribute” <id> <constant> <eol>
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- [ ] <sigspec> ::= <constant> | <wire-id> | <sigspec> “[” <integer> (“:” <integer>)? “]” | “{” <sigspec>* “}”
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- [ ] <conn-stmt> ::= “connect” <sigspec> <sigspec> <eol>
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- [ ] <wire> ::= <attr-stmt>* <wire-stmt>
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- [ ] <wire-stmt> ::= “wire” <wire-option>* <wire-id> <eol>
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- [ ] <wire-id> ::= <id>
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- [ ] <wire-option> ::= “width” <integer> | “offset” <integer> | “input” <integer> | “output” <integer> | “inout” <integer> | “upto” | “signed”
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- [x] <sigspec> ::= <constant> | <wire-id> | <sigspec> “[” <integer> (“:” <integer>)? “]” | “{” <sigspec>* “}”
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- [x] <conn-stmt> ::= “connect” <sigspec> <sigspec> <eol>
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- [x] <wire> ::= <attr-stmt>* <wire-stmt>
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- [x] <wire-stmt> ::= “wire” <wire-option>* <wire-id> <eol>
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- [x] <wire-id> ::= <id>
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- [x] <wire-option> ::= “width” <integer> | “offset” <integer> | “input” <integer> | “output” <integer> | “inout” <integer> | “upto” | “signed”
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- [ ] <memory> ::= <attr-stmt>* <memory-stmt>
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- [ ] <memory-stmt> ::= “memory” <memory-option>* <id> <eol>
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- [ ] <memory-option> ::= “width” <integer> | “size” <integer> | “offset” <integer>
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@ -10,6 +10,7 @@ let
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haskellPackages.filepath
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haskellPackages.pretty-show
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haskellPackages.prettyprinter
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haskellPackages.pretty-show
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];
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in
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haskellPackages.mkDerivation {
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@ -86,6 +86,7 @@ executable rtlil-parse
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-- Other library packages from which modules are imported.
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build-depends:
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base ^>=4.17.2.1,
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pretty-show >=1.6,
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haskellator
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-- Directories containing source files.
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@ -1,9 +1,12 @@
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module RTLILParser.AST(
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AutoIdxStmt(..), ParamStmt(..), AutogenId(..),
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Constant(..), CellStmt(..), PublicId(..),
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AttrStmt(..), Value(..), Id(..),
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CellId(..), CellType(..), WireId(..),
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SigSpec(..), Slice(..)
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AutoIdxStmt(..) ,ParamStmt(..) ,AutogenId(..)
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,Constant(..) ,CellStmt(..) ,PublicId(..)
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,AttrStmt(..) ,Value(..) ,Id(..)
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,CellId(..) ,CellType(..) ,WireId(..)
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,SigSpec(..) ,Slice(..) ,ConnStmt(..)
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,WireOption(..) ,WireStmt(..) ,Wire(..)
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,MemoryOption(..) ,MemoryStmt(..) ,Memory(..)
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,MemoryID(..)
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) where
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import Text.Read (Lexeme(Ident))
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import Data.Functor.Contravariant (Contravariant)
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@ -15,13 +18,30 @@ data Slice = Slice Int (Maybe Int) deriving (Show)
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data Id = Public PublicId
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| Autogen AutogenId
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deriving (Show)
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data WireId = WireId Id
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deriving (Show)
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data WireId = WireId Id deriving (Show)
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data MemoryID = MemoryID Id deriving (Show)
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data AutoIdxStmt = AutoIdxStmt Int deriving (Show)
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data AttrStmt = AttrStmt Id Constant deriving (Show)
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data CellStmt = CellStmt CellId CellType deriving (Show)
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data CellId = CellId Id deriving (Show)
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data CellType = CellType Id deriving (Show)
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data AttrStmt = AttrStmt Id Constant deriving (Show)
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data CellStmt = CellStmt CellId CellType deriving (Show)
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data CellId = CellId Id deriving (Show)
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data CellType = CellType Id deriving (Show)
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data ConnStmt = ConnStmt SigSpec SigSpec deriving (Show)
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data WireOption = WireOptionWidth Int
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| WireOptionOffset Int
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| WireOptionInput Int
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| WireOptionOutput Int
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| WireOptionInout Int
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| WireOptionUpto
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| WireOptionSigned
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deriving (Show)
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data WireStmt = WireStmt WireId [WireOption] deriving (Show)
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data Wire = Wire WireStmt [AttrStmt] deriving (Show)
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data MemoryOption = MemoryOptionWidth Int
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| MemoryOptionSize Int
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| MemoryOptionOffset Int
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deriving (Show)
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data MemoryStmt = MemoryStmt MemoryID [MemoryOption] deriving (Show)
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data Memory = Memory MemoryStmt [AttrStmt] deriving (Show)
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data SigSpec = SigSpecConstant Constant
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| SigSpecWireId WireId
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| SigSpecSlice SigSpec Slice
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@ -7,11 +7,14 @@ import Control.Monad (void)
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import Text.Parsec
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import Text.Parsec.String (Parser)
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import RTLILParser.AST(
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AutoIdxStmt(..), ParamStmt(..), AutogenId(..),
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Constant(..), CellStmt(..), PublicId(..),
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AttrStmt(..), Value(..), Id(..),
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CellId(..), CellType(..), WireId(..),
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SigSpec(..), Slice(..)
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AutoIdxStmt(..) ,ParamStmt(..) ,AutogenId(..)
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,Constant(..) ,CellStmt(..) ,PublicId(..)
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,AttrStmt(..) ,Value(..) ,Id(..)
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,CellId(..) ,CellType(..) ,WireId(..)
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,SigSpec(..) ,Slice(..) ,ConnStmt(..)
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,WireOption(..) ,WireStmt(..) ,Wire(..)
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,MemoryOption(..) ,MemoryStmt(..) ,Memory(..)
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,MemoryID(..)
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)
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import Util(binaryStringToInt)
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import RTLILParser.Primitives(pEscapedChar)
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@ -141,6 +144,59 @@ pSigSpec =
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try pSigSpecConcat -- Check for concatenation first
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<|> pSingleSigSpec -- Otherwise parse a single sigspec
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pConnStmt :: Parser ConnStmt
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pConnStmt = ConnStmt
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<$> (string "connect" *> pWs *> pSigSpec)
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<*> (pWs *> pSigSpec)
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<* pEol
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pWireOption :: Parser WireOption
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pWireOption =
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try (WireOptionWidth <$> (string "width" *> pWs *> pInteger)) <|>
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try (WireOptionOffset <$> (string "offset" *> pWs *> pInteger)) <|>
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try (WireOptionInput <$> (string "input" *> pWs *> pInteger)) <|>
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try (WireOptionOutput <$> (string "output" *> pWs *> pInteger)) <|>
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try (WireOptionInout <$> (string "inout" *> pWs *> pInteger)) <|>
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(string "upto" *> return WireOptionUpto) <|>
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(string "signed" *> return WireOptionSigned)
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pWireStmt :: Parser WireStmt
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pWireStmt =
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WireStmt
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<$ string "wire"
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<* pWs
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<*> (WireId <$> pId)
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<* pWs
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<*> many pWireOption
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<* pEol
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pWire :: Parser Wire
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pWire = do
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attrs <- many pAttrStmt
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wireStmt <- pWireStmt
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return $ Wire wireStmt attrs
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pMemoryOption :: Parser MemoryOption
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pMemoryOption =
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try (MemoryOptionWidth <$> (string "width" *> pWs *> pInteger)) <|>
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try (MemoryOptionSize <$> (string "size" *> pWs *> pInteger)) <|>
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try (MemoryOptionOffset <$> (string "offset" *> pWs *> pInteger))
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pMemoryStmt :: Parser MemoryStmt
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pMemoryStmt =
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MemoryStmt
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<$ string "memory"
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<* pWs
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<*> (MemoryID <$> pId)
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<* pWs
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<*> many pMemoryOption
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<* pEol
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pMemory :: Parser Memory
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pMemory = do
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attrs <- many pAttrStmt
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memoryStmt <- pMemoryStmt
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return $ Memory memoryStmt attrs
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-- would correspond to `123456789[0:9][0:8]`
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exampleSigSpecSlice =
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