Artturin/RiscV-Formal
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9 commits

Author SHA1 Message Date
Yehowshua Immanuel c8b192cade prep for notable re-org 2025-02-26 02:24:23 -05:00
Yehowshua Immanuel 024115e389 Uart now has correct write implementation presumably 2025-02-26 01:51:33 -05:00
Yehowshua Immanuel 8d5cd862ab more progress on UART read 2025-02-25 23:47:00 -05:00
Yehowshua Immanuel 7265728932 read getting closer to being done 2025-02-25 19:09:37 -05:00
Yehowshua Immanuel 1f9bd2f015 hopefully progressing to a more scalable bus architecture 2025-02-25 14:24:54 -05:00
Yehowshua Immanuel 003a1c8545 works even better now 2025-02-19 18:28:08 -05:00
Yehowshua Immanuel f9248057f9 getting closer... 2025-02-19 09:06:40 -05:00
Yehowshua Immanuel 32932f4816 added basic decoding 2025-02-19 01:21:02 -05:00
Yehowshua Immanuel ef58d5b07e first commit 2025-02-12 23:54:15 -05:00