RiscV-Formal/hs
2025-02-26 01:51:33 -05:00
..
Isa works even better now 2025-02-19 18:28:08 -05:00
Peripherals Uart now has correct write implementation presumably 2025-02-26 01:51:33 -05:00
Bus.hs Uart now has correct write implementation presumably 2025-02-26 01:51:33 -05:00
BusTypes.hs read getting closer to being done 2025-02-25 19:09:37 -05:00
Fetch.hs more progress on UART read 2025-02-25 23:47:00 -05:00
Machine.hs more progress on UART read 2025-02-25 23:47:00 -05:00
RegFiles.hs first commit 2025-02-12 23:54:15 -05:00
Simulation.hs more progress on UART read 2025-02-25 23:47:00 -05:00
Types.hs hopefully progressing to a more scalable bus architecture 2025-02-25 14:24:54 -05:00
Util.hs first commit 2025-02-12 23:54:15 -05:00