forked from Yehowshua/RiscV-Formal
added basic decoding
This commit is contained in:
parent
ef58d5b07e
commit
32932f4816
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@ -1,52 +0,0 @@
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{-# LANGUAGE DataKinds #-}
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{-# LANGUAGE NumericUnderscores #-}
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module Decode.Opcodes(Opcode(..)) where
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import Clash.Prelude
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import Data.Functor.Contravariant (Op)
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type FUNCT7 = Unsigned 7
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type RS2 = Unsigned 5
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type RS1 = Unsigned 5
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type FUNCT3 = Unsigned 3
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type RD = Unsigned 5
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type OPCODE = Unsigned 7
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type IMM12 = Unsigned 12
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type IMM13 = Unsigned 13
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type IMM20 = Unsigned 20
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type IMM21 = Unsigned 21
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data RTypeFields = RTypeFields OPCODE RD FUNCT3 RS1 RS2 FUNCT7
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data ITypeFields = ITypeFields OPCODE RD FUNCT3 RS1 IMM12
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data STypeFields = STypeFields OPCODE FUNCT3 RS1 RS2 IMM12
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data BTypeFields = BTypeFields OPCODE FUNCT3 RS1 RS2 IMM13
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data UTypeFields = UTypeFields OPCODE RD IMM20
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data JTypeFields = JTypeFields OPCODE RD IMM21
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data Opcode
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= ADD RTypeFields
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| SUB RTypeFields
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| XOR RTypeFields
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| OR RTypeFields
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| AND RTypeFields
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| SLL RTypeFields
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| SRL RTypeFields
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| SRA RTypeFields
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| SLT RTypeFields
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| SLTU RTypeFields
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| ADDRI ITypeFields
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| XORI ITypeFields
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| ORI ITypeFields
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| ANDI ITypeFields
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| SLLI ITypeFields
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| SRLI ITypeFields
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| SRAI ITypeFields
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| SLTI ITypeFields
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| SLTIU ITypeFields
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| LB ITypeFields
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| LH ITypeFields
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| LW ITypeFields
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| LBU ITypeFields
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| LHU ITypeFields
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@ -4,13 +4,13 @@
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module Fetch(fetchInstruction) where
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import Clash.Prelude
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import Types(Mem, Addr, FullWord)
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import Types(Mem, Addr, Insn)
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import Util(endianSwapWord)
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data Insn = Instruction FullWord
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| Misaligned Addr
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data FetchResult = Instruction Insn
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| Misaligned Addr
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fetchInstruction :: KnownNat n => Mem n -> Addr -> Insn
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fetchInstruction :: KnownNat n => Mem n -> Addr -> FetchResult
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fetchInstruction mem addr =
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let
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isWordAligned = addr .&. 3 == 0
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192
hs/Isa/Decode.hs
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192
hs/Isa/Decode.hs
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@ -0,0 +1,192 @@
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{-# LANGUAGE DataKinds #-}
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{-# LANGUAGE NumericUnderscores #-}
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module Isa.Decode(decode) where
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import Isa.Forms(
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FUNCT7, RS2, RS1, FUNCT3, RD, OPCODE,
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IMM12, IMM13, IMM20, IMM21,
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RTypeFields(..), ITypeFields(..), STypeFields(..),
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BTypeFields(..), UTypeFields(..), JTypeFields(..),
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Opcode(..)
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)
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import Clash.Prelude
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import Data.Functor.Contravariant (Op)
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import Types(Mem, Addr, Insn)
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import Distribution.Backpack.FullUnitId (FullDb)
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getOpcode :: Insn -> Unsigned 7
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getOpcode instr = bitCoerce $ slice d6 d0 (pack instr)
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getImm12 :: Insn -> Unsigned 12
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getImm12 instr = bitCoerce $ slice d31 d20 (pack instr)
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getImm12SType :: Insn -> Unsigned 12
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getImm12SType instr = bitCoerce $ immediateUpper ++# immediateLower
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where
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immediateUpper = (slice d31 d25 (pack instr))
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immediateLower = (slice d11 d7 (pack instr))
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getImm20UType :: Insn -> Unsigned 20
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getImm20UType instr = bitCoerce $ slice d31 d12 (pack instr)
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getImm13BType :: Insn -> Unsigned 13
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getImm13BType instr = bitCoerce $ imm12 ++# imm10_5 ++# imm4_1 ++# imm11 ++# zero
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where
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imm12 = slice d31 d31 (pack instr) -- imm[12]
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imm10_5 = slice d30 d25 (pack instr) -- imm[10:5]
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imm4_1 = slice d11 d8 (pack instr) -- imm[4:1]
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imm11 = slice d7 d7 (pack instr) -- imm[11]
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zero = 0 :: BitVector 1 -- LSB always zero for B-type
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getFunct3 :: Insn -> Unsigned 3
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getFunct3 instr = bitCoerce $ slice d14 d12 (pack instr)
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getFunct7 :: Insn -> Unsigned 7
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getFunct7 instr = bitCoerce $ slice d31 d25 (pack instr)
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getRd :: Insn -> Unsigned 5
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getRd instr = bitCoerce $ slice d11 d7 (pack instr)
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getRs2 :: Insn -> Unsigned 5
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getRs2 instr = bitCoerce $ slice d24 d20 (pack instr)
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getRs1 :: Insn -> Unsigned 5
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getRs1 instr = bitCoerce $ slice d19 d15 (pack instr)
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decodeRType :: Insn -> Opcode
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decodeRType insn =
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case funct3 of
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0x00 -> ADD (RTypeFields opcode rd funct3 rs1 rs2 funct7)
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0x00 -> SUB (RTypeFields opcode rd funct3 rs1 rs2 funct7)
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0x04 -> XOR (RTypeFields opcode rd funct3 rs1 rs2 funct7)
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0x06 -> OR (RTypeFields opcode rd funct3 rs1 rs2 funct7)
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0x07 -> AND (RTypeFields opcode rd funct3 rs1 rs2 funct7)
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0x01 -> SLL (RTypeFields opcode rd funct3 rs1 rs2 funct7)
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0x05 -> SRL (RTypeFields opcode rd funct3 rs1 rs2 funct7)
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0x05 -> SRA (RTypeFields opcode rd funct3 rs1 rs2 funct7)
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0x02 -> SLT (RTypeFields opcode rd funct3 rs1 rs2 funct7)
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0x03 -> SLTU (RTypeFields opcode rd funct3 rs1 rs2 funct7)
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_ -> Unimplemented
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where
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opcode = getOpcode insn
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rd = getRd insn
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funct3 = getFunct3 insn
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rs1 = getRs1 insn
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rs2 = getRs2 insn
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funct7 = getFunct7 insn
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decodeIType :: Insn -> Opcode
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decodeIType insn = case opcode of
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0b0010011 -> case funct3 of
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0x0 -> ADDI (ITypeFields opcode rd funct3 rs1 imm)
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0x4 -> XORI (ITypeFields opcode rd funct3 rs1 imm)
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0x6 -> ORI (ITypeFields opcode rd funct3 rs1 imm)
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0x7 -> ANDI (ITypeFields opcode rd funct3 rs1 imm)
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0x1 -> if slice d31 d25 (pack insn) == 0
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then SLLI (ITypeFields opcode rd funct3 rs1 imm)
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else Unimplemented
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0x5 -> case slice d31 d25 (pack insn) of -- Distinguish SRLI and SRAI
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0x00 -> SRLI (ITypeFields opcode rd funct3 rs1 imm)
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0x20 -> SRAI (ITypeFields opcode rd funct3 rs1 imm)
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_ -> Unimplemented
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0x2 -> SLTI (ITypeFields opcode rd funct3 rs1 imm)
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0x3 -> SLTIU (ITypeFields opcode rd funct3 rs1 imm)
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_ -> Unimplemented
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0b0000011 -> case funct3 of
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0x0 -> LB (ITypeFields opcode rd funct3 rs1 imm)
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0x1 -> LH (ITypeFields opcode rd funct3 rs1 imm)
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0x2 -> LW (ITypeFields opcode rd funct3 rs1 imm)
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0x4 -> LBU (ITypeFields opcode rd funct3 rs1 imm)
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0x5 -> LHU (ITypeFields opcode rd funct3 rs1 imm)
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_ -> Unimplemented
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0b1100111 -> case funct3 of
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0x0 -> JALR (ITypeFields opcode rd funct3 rs1 imm)
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_ -> Unimplemented
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0b1110011 -> case imm of
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0x000 -> ECALL (ITypeFields opcode rd funct3 rs1 imm)
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0x001 -> EBREAK (ITypeFields opcode rd funct3 rs1 imm)
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_ -> Unimplemented
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_ -> Unimplemented
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where
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opcode = getOpcode insn
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rd = getRd insn
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funct3 = getFunct3 insn
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rs1 = getRs1 insn
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imm = getImm12 insn
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decodeSType :: Insn -> Opcode
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decodeSType insn = case funct3 of
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0x0 -> SB (STypeFields opcode funct3 rs1 rs2 imm12) -- Store Byte
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0x1 -> SH (STypeFields opcode funct3 rs1 rs2 imm12) -- Store Halfword
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0x2 -> SW (STypeFields opcode funct3 rs1 rs2 imm12) -- Store Word
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_ -> Unimplemented
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where
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opcode = getOpcode insn
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funct3 = getFunct3 insn
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rs1 = getRs1 insn
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rs2 = getRs2 insn
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imm12 = getImm12SType insn
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decodeBType :: Insn -> Opcode
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decodeBType insn = case funct3 of
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0x0 -> BEQ (BTypeFields opcode funct3 rs1 rs2 imm13) -- Branch if equal
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0x1 -> BNE (BTypeFields opcode funct3 rs1 rs2 imm13) -- Branch if not equal
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0x4 -> BLT (BTypeFields opcode funct3 rs1 rs2 imm13) -- Branch if less than
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0x5 -> BGE (BTypeFields opcode funct3 rs1 rs2 imm13) -- Branch if greater or equal
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0x6 -> BLTU (BTypeFields opcode funct3 rs1 rs2 imm13) -- Branch if less than (unsigned)
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0x7 -> BGEU (BTypeFields opcode funct3 rs1 rs2 imm13) -- Branch if greater or equal (unsigned)
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_ -> Unimplemented
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where
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opcode = getOpcode insn
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funct3 = getFunct3 insn
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rs1 = getRs1 insn
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rs2 = getRs2 insn
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imm13 = getImm13BType insn
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decodeUType :: Insn -> Opcode
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decodeUType insn = case opcode of
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0b0110111 -> LUI (UTypeFields opcode rd imm20) -- LUI
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0b0010111 -> AUIPC (UTypeFields opcode rd imm20) -- AUIPC
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_ -> Unimplemented
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where
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opcode = getOpcode insn
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rd = getRd insn
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imm20 = getImm20UType insn
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getImm21JType :: Insn -> Unsigned 21
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getImm21JType instr = bitCoerce $ imm20 ++# imm10_1 ++# imm11 ++# imm19_12 ++# zero
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where
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imm20 = slice d31 d31 (pack instr) -- imm[20]
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imm10_1 = slice d30 d21 (pack instr) -- imm[10:1]
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imm11 = slice d20 d20 (pack instr) -- imm[11]
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imm19_12 = slice d19 d12 (pack instr) -- imm[19:12]
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zero = 0 :: BitVector 1 -- LSB always zero for J-type
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decodeJType :: Insn -> Opcode
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decodeJType insn = case getOpcode insn of
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0b1101111 -> JAL (JTypeFields opcode rd imm21) -- JAL
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_ -> Unimplemented
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where
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opcode = getOpcode insn
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rd = getRd insn
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imm21 = getImm21JType insn
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orElse :: Opcode -> Opcode -> Opcode
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orElse Unimplemented y = y
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orElse x _ = x
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decode :: Insn -> Opcode
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decode insn =
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decodeRType insn `orElse`
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decodeIType insn `orElse`
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decodeSType insn `orElse`
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decodeBType insn `orElse`
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decodeUType insn `orElse`
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decodeJType insn
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89
hs/Isa/Forms.hs
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89
hs/Isa/Forms.hs
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@ -0,0 +1,89 @@
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{-# LANGUAGE DataKinds #-}
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{-# LANGUAGE NumericUnderscores #-}
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module Isa.Forms(
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FUNCT7, RS2, RS1, FUNCT3, RD, OPCODE,
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IMM12, IMM13, IMM20, IMM21,
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RTypeFields(..), ITypeFields(..), STypeFields(..),
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BTypeFields(..), UTypeFields(..), JTypeFields(..),
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Opcode(..)
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) where
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import Clash.Prelude
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import Types(Mem, Addr, Insn)
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type FUNCT7 = Unsigned 7
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type RS2 = Unsigned 5
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type RS1 = Unsigned 5
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type FUNCT3 = Unsigned 3
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type RD = Unsigned 5
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type OPCODE = Unsigned 7
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type IMM12 = Unsigned 12
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type IMM13 = Unsigned 13
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type IMM20 = Unsigned 20
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type IMM21 = Unsigned 21
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data RTypeFields = RTypeFields OPCODE RD FUNCT3 RS1 RS2 FUNCT7 deriving (Generic, Show, Eq, NFDataX)
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data ITypeFields = ITypeFields OPCODE RD FUNCT3 RS1 IMM12 deriving (Generic, Show, Eq, NFDataX)
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data STypeFields = STypeFields OPCODE FUNCT3 RS1 RS2 IMM12 deriving (Generic, Show, Eq, NFDataX)
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data BTypeFields = BTypeFields OPCODE FUNCT3 RS1 RS2 IMM13 deriving (Generic, Show, Eq, NFDataX)
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data UTypeFields = UTypeFields OPCODE RD IMM20 deriving (Generic, Show, Eq, NFDataX)
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data JTypeFields = JTypeFields OPCODE RD IMM21 deriving (Generic, Show, Eq, NFDataX)
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data Opcode
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=
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-- R-Type
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ADD RTypeFields
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| SUB RTypeFields
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| XOR RTypeFields
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| OR RTypeFields
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| AND RTypeFields
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| SLL RTypeFields
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| SRL RTypeFields
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| SRA RTypeFields
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| SLT RTypeFields
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| SLTU RTypeFields
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-- I-Type
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| ADDI ITypeFields
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| XORI ITypeFields
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| ORI ITypeFields
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| ANDI ITypeFields
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| SLLI ITypeFields
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| SRLI ITypeFields
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| SRAI ITypeFields
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| SLTI ITypeFields
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| SLTIU ITypeFields
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| LB ITypeFields
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| LH ITypeFields
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| LW ITypeFields
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| LBU ITypeFields
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| LHU ITypeFields
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| ECALL ITypeFields
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| EBREAK ITypeFields
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-- S-Type
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| SB STypeFields
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| SH STypeFields
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| SW STypeFields
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-- B-Type
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| BEQ BTypeFields
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| BNE BTypeFields
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| BLT BTypeFields
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| BGE BTypeFields
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| BLTU BTypeFields
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| BGEU BTypeFields
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-- J-Type
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| JAL JTypeFields
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| JALR ITypeFields
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-- U-Type
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| LUI UTypeFields
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| AUIPC UTypeFields
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| Unimplemented
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deriving (Generic, Show, Eq, NFDataX)
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@ -47,9 +47,6 @@ machine' machine =
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in
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machine { cpu = cpu', mem = mem' }
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machineSignal :: HiddenClockResetEnable dom => Signal dom Machine
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machineSignal = register machine (machine' <$> machineSignal)
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simulationLoop :: Int -> Machine -> IO [Machine]
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simulationLoop 0 state = return [state]
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simulationLoop n state = do
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@ -1,7 +1,7 @@
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{-# LANGUAGE DataKinds #-}
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{-# LANGUAGE NumericUnderscores #-}
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module Types(Pc, BusVal(..), Mem, FullWord, Addr) where
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module Types(Pc, BusVal(..), Mem, FullWord, Insn, Addr) where
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import Clash.Prelude
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@ -10,6 +10,7 @@ type HalfWord = Unsigned 16
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type FullWord = Unsigned 32
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type DoubleWord = Unsigned 64
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type QuadWord = Unsigned 128
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type Insn = FullWord
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data BusVal
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= BusByte Byte
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@ -87,7 +87,8 @@ library
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exposed-modules:
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Simulation
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other-modules:
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Decode.Opcodes,
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Isa.Decode,
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Isa.Forms,
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Peripherals.Ram,
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Peripherals.UartCFFI,
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Peripherals.Setup,
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