Yehowshua
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Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-10 21:23:43 +00:00
ad751a5039 read is getting there...
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-08 03:04:45 +00:00
171fcece98 reduce debug in sim and add PREFIX to makefile
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-08 02:41:50 +00:00
63a73d3f71 now fetching from ram correctly as ram is 32 bit word not byte indexed
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-08 01:31:45 +00:00
3f50fe32f8 still compiling after refactoring field types
Yehowshua commented on issue Yehowshua/RiscV-Formal#12 2025-03-08 00:12:07 +00:00
Make CSR Content Addressable

The closest we can get to "CSR does not exist" is perhaps "Illegal Instruction Exception"

Yehowshua opened issue Yehowshua/RiscV-Formal#12 2025-03-08 00:10:54 +00:00
Make CSR Content Addressable
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-07 23:41:59 +00:00
73d5e1204c stopping point before re-factoring decoder types
6b81cd28ee working on adding read stage
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Yehowshua closed issue Yehowshua/RiscV-Formal#2 2025-03-06 13:49:56 +00:00
Generalize Memory Access
Yehowshua commented on issue Yehowshua/RiscV-Formal#2 2025-03-06 13:49:56 +00:00
Generalize Memory Access

done

Yehowshua closed issue Yehowshua/RiscV-Formal#11 2025-03-06 13:49:22 +00:00
Replace $ with custom |> operator
Yehowshua commented on issue Yehowshua/RiscV-Formal#11 2025-03-06 13:49:22 +00:00
Replace $ with custom |> operator

Resolved as of 4cc8c8d430

Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-06 13:44:43 +00:00
4cc8c8d430 Forgot to replace $ operator in Uart.hs
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-06 13:41:30 +00:00
0792bf3c7d Replacing $ operator with more readable |> operator
Yehowshua opened issue Yehowshua/RiscV-Formal#11 2025-03-05 14:07:02 +00:00
Replace $ with custom `
Yehowshua opened issue Yehowshua/RiscV-Formal#10 2025-03-05 14:06:09 +00:00
Probably more useful to have Add instead of Insn in IllegalInstruction Exception variant
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-05 14:05:19 +00:00
2b1c486c17 created Decode result
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-05 05:11:02 +00:00
a6c435791a improve instructions to simulate in README
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-05 05:09:11 +00:00
7f7ba49ee1 prune more warnings and re-org Decode files a bit
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-05 04:54:37 +00:00
67b44dedc0 clean up warnings a bit
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-05 04:43:48 +00:00
30650b870c replace/update relevant fetch types and functions