FastWaveBackend/tests/vcd-files/sources.csv

1	Icarus	https://github.com/dpretet/vcd/blob/master/test1.vcd	https://github.com/ombhilare999/riscv-core/blob/master/src/rv32_soc_TB.vcd	https://github.com/b06902044/computer_architecture/blob/main/CPU.vcd
2	Verilator	https://github.com/wavedrom/vcd-samples/blob/trunk/swerv1.vcd	https://github.com/bigBrain1901/nPOWER-ISA-5-STAGE-PIPELINED-CPU/blob/master/post_compile_files/vlt_dump.vcd
3	GHDL	https://raw.githubusercontent.com/AdoobII/idea_21s/main/vhdl/idea.vcd	https://github.com/gaoqqt2n/CPU/blob/master/SuperPipelineCPU/vcdfile/pcpu.vcd	https://github.com/charlycop/VLSI-1/blob/master/EXEC/ALU/alu.vcd
4	VCS	https://raw.githubusercontent.com/ameyjain/8-bit-Microprocessor/master/8-bit%20microprocessor/processor.vcd	https://raw.githubusercontent.com/Akashay-Singla/RISC-V/main/Pipeline/datapath_log.vcd	https://raw.githubusercontent.com/sathyapriyanka/APB_UVC_UVM/main/Apb_slave_uvm_new.vcd
5	QuestaSim	https://github.com/mr-gaurav/Sequence-Counter/blob/main/test.vcd	https://github.com/SparshAgarwal/Computer-Architecture/blob/master/hw3/hw3_1/dump.vcd
6	ModelSim	https://github.com/Mohammad-Heydariii/Digital-Systems-Lab-Course/blob/main/Lab_project4/modelsim_files/clkdiv2n_tb.vcd	https://github.com/sh619/Songyu_Huang-Chisel/blob/main/MU0_final_version/simulation/qsim/CPU_Design.msim.vcd
7	Quartus	https://github.com/PedroTLemos/ProjetoInfraHard/blob/master/mipsHardware.vcd
8	SystemC	https://github.com/jroslindo/Mips-Systemc/blob/main/REGISTRADORES_32_bits/wave_registradores.vcd	https://github.com/amrhas/PDRNoC/blob/VCRouter/noctweak/Debug/waveform.vcd.vcd
9	Treadle	https://github.com/chipsalliance/treadle/blob/master/src/test/resources/GCD.vcd
10	Aldec	https://github.com/SVeilleux9/FPGA-GPIO-Extender/blob/main/Firmware/aldec/SPI_Write/SPI_Write.vcd
11	Riviera-PRO	https://github.com/prathampathak/Tic-Tac-Tao/blob/main/dump.vcd
12	MyHDL	https://github.com/aibtw/myHdl_Projects/blob/main/SimpleMemory/Simple_Memory.vcd	https://github.com/Abhishek010397/Programming-RISC-V/blob/master/top.vcd	https://github.com/DarthSkipper/myHDL_Sigmoid/blob/master/out/testbench/sigmoid_tb.vcd
13	ncsim	https://github.com/amiteee78/RTL_design/blob/master/ffdiv_32bit/ffdiv_32bit_prop_binom/run_cad/ffdiv_32bit_tb.vcd
14	xilinx_isim	https://github.com/mukul54/qrs-peak-fpga/blob/master/utkarsh/utkarsh.sim/sim_1/behav/xsim/test.vcd	https://github.com/DanieleParravicini/regex_coprocessor/blob/master/scripts/sim/test2x2_regex22_string1.vcd	https://github.com/pabloec1729/Hashes-generator/blob/master/RTL/velocidad/test.vcd
15	vivado	https://github.com/saharmalmir/Eth2Ser/blob/master/UART2ETH.runs/impl_1/iladata.vcd	https://github.com/BradMcDanel/multiplication-free-dnn/blob/master/verilog/iladata.vcd
16	GTKWave-Analyzer	https://github.com/Asfagus/Network-Switch/blob/main/perm_current.vcd
17	Amaranth	Locally Simulated File