55 lines
1.9 KiB
Markdown
55 lines
1.9 KiB
Markdown
# MannaChip
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## Introduction:
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Manna was the miraculous food provided by God requiring no effort on behalf of the Israelites. In a similar vein, the MannaChip processor delivers groundbreaking performance, necessitating minimal intervention on the developer's or user's part.
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Just as "man does not live by bread alone, but by every word that proceeds from the mouth of God," this chip thrives on every instruction word you provide. It's not just about raw computational power, but the synergy between user input and hardware optimization.
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``TOPMODULE=mkTop make v_compile`` to generate verilog. The generated verilog can
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be found in the ``verilog_RTL/`` folder.
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# Status
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Admittedly, not very far. Perhaps one could say we've got the beginnings
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of what would make for LED and UART controllers.
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# Dependencies
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## Linux
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Running `nix-shell` should *just work* on Linux. To be fair, haven't
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tested this yet.
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## MacOS
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Upstream nix recipes need to be adjusted a bit to work on MacOS, so
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for now do:
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1. [Yosys](https://github.com/YosysHQ/yosys) at git commit: 7ce5011c24b
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2. [nextpnr-0.4-36-gc8406b71](https://github.com/YosysHQ/nextpnr)
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3. [PrjTrellis](https://github.com/YosysHQ/prjtrellis) at git commit: 1.2.1-22-g35f5aff
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4. [openFPGALoader](https://github.com/trabucayre/openFPGALoader)
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# Programming the ULX3S
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```bash
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make fpga
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# You may need the following line to set your screen device config
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# to one parity and one stop bit. Tested working on MacOS, should
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# work on Linux.
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stty -f /dev/tty.usbserial-K00027 -cstopb -parenb
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screen /dev/tty.usbserial-K00027 9600
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```
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# Simulation
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## Main Chip Core
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TODO
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## Experiments
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See experiments README.
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# Generating Verilog
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```bash
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TOPMODULE=mkTop make v_compile
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```
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# TODO
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- [ ] debug UART accuracy
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- clk divider should be frequency matched
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# Notable Reference Files
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``/Users/yehowshuaimmanuel/git/bsc/testsuite/bsc.bsv_examples/cpu/FiveStageCPUQ3sol.bsv`` |