52 lines
1.3 KiB
Haskell
52 lines
1.3 KiB
Haskell
package Serializer(
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mkSerialize,
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ISerializer(..),
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State(..))
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where
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import ClkDivider
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import State
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serialize :: State -> Bit 8 -> Bit 1
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serialize ftdiState dataReg =
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case ftdiState of
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START -> 1'b0
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(DATA n) -> dataReg[n:n]
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_ -> 1'b1
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interface (ISerializer :: # -> # -> *) clkFreq baudRate =
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putBit8 :: (Bit 8) -> Action {-# always_enabled, always_ready #-}
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bitLineOut :: Bit 1 {-# always_ready #-}
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mkSerialize :: Handle -> Module (ISerializer clkFreq baudRate)
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mkSerialize fileHandle = do
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ftdiTxOut :: Wire(Bit 1) <- mkBypassWire
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dataReg :: Reg(Bit 8) <- mkReg(0)
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ftdiState <- mkReg(IDLE)
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clkDivider :: (ClkDivider (TDiv clkFreq baudRate)) <- mkClkDivider fileHandle
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addRules $
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rules
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{-# ASSERT fire when enabled #-}
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"ADVANCE UART STATE WHEN NOT IDLE" : when
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(ftdiState /= IDLE),
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(clkDivider.isAdvancing) ==>
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do
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ftdiState := ftdiStateNext ftdiState
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{-# ASSERT fire when enabled #-}
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"BIT LINE" : when True ==>
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do
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ftdiTxOut := serialize ftdiState dataReg
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return $
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interface ISerializer
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putBit8 bit8Val =
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do
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clkDivider.reset
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dataReg := bit8Val
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ftdiState := ftdiStateNext ftdiState
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when (ftdiState == IDLE)
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bitLineOut = ftdiTxOut
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