first commit

.gitignore

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+*.vcd
+*.so

Makefile

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+###  -*-Makefile-*-
+# Copyright (c) 2016-2020 Bluespec, Inc.  All Rights Reserved.
+
+# ================================================================
+# This is an example Makefile for the examples in this tutorial
+
+# You should only have to edit the variable definitions in the
+# following section (or override them from the 'make' command line)
+
+# Your PATH should include the directory where your 'bsc' binary lives
+# For example, if you cloned:
+#     https://github.com/B-Lang-org/bsc
+# into
+#     ~/git_clones/bsc
+# and built 'bsc' there using the standard 'make all', you'd add
+#     ~/git_clones/bsc/inst/bin
+# to your PATH
+#
+# Do 'bsc -v' or 'bsc -help' to test that you can invoke bsc.
+
+# ================================================================
+# Please modify the following for your installation and setup
+
+# Directory containing this tutorial
+TUTORIAL ?= ..
+
+# Set this to the command that invokes your Verilog simulator
+# V_SIM ?= verilator
+# V_SIM ?= iverilog
+# V_SIM ?= cvc
+# V_SIM ?= cver
+# V_SIM ?= vcsi
+# V_SIM ?= vcs
+# V_SIM ?= modelsim
+# V_SIM ?= ncsim
+# V_SIM ?= ncverilog
+
+ifeq ($(V_SIM),verilator)
+  V_SIM += -Xv --no-timing
+endif
+
+# ================================================================
+# You should not have to change anything below this line
+
+RESOURCES_DIR ?= $(TUTORIAL)/Resources
+
+TOPLANG ?= BH
+
+ifeq ($(TOPLANG),BSV)
+  SRC_EXT=bsv
+else ifeq ($(TOPLANG),BH)
+  SRC_EXT=bs
+else
+  SRC_EXT=TOPLANG_NOT_DEFINED
+endif
+
+TOPFILE   ?= src/Top.$(SRC_EXT)
+TOPMODULE ?= mkTop
+
+BSC_COMP_FLAGS += \
+		-keep-fires  \
+		-aggressive-conditions  \
+		-no-warn-action-shadowing  \
+		-check-assert  \
+		-cpp \
+		-show-schedule \
+		+RTS -K128M -RTS  -show-range-conflict \
+		$(BSC_COMP_FLAG1)  $(BSC_COMP_FLAG2)  $(BSC_COMP_FLAG3)
+
+BSC_LINK_FLAGS += -keep-fires
+
+BSC_PATHS = -p src/:+
+
+.PHONY: help
+help:
+	@echo ""
+	@echo "Targets for 'make':"
+	@echo "    help                Print this information"
+	@echo ""
+	@echo "    Bluesim:"
+	@echo "        b_compile       Compile for Bluesim"
+	@echo "        b_link          Link a Bluesim executable"
+	@echo "        b_sim           Run the Bluesim simulation executable"
+	@echo "        b_all           Convenience for 'make b_compile b_link b_sim'"
+	@echo "        b_sim_vcd       Run the Bluesim simulation executable and generate VCD"
+	@echo ""
+	@echo "    Verilog generation and Verilog sim:"
+	@echo "        v_compile       Compile for Verilog (Verilog files generated in verilog_RTL/)"
+	@echo "        v_link          Link a Verilog simulation executable"
+	@echo "                            (current simulator:" $(V_SIM) " (redefine V_SIM for other Verilog simulators)"
+	@echo "        v_sim           Run the Verilog simulation executable"
+	@echo "        v_all           Convenience for 'make v_compile v_link v_sim'"
+	@echo "        v_sim_vcd       Run the Verilog simulation executable and dump VCD"
+	@echo ""
+	@echo "    clean               Delete intermediate files in build_b_sim/ and build_v/ dirs"
+	@echo "    full_clean          Delete all but this Makefile"
+
+# ================================================================
+# Bluesim compile/link/simulate
+
+B_SIM_DIRS = -simdir build_b_sim -bdir build_b_sim -info-dir build_b_sim
+B_SIM_EXE = $(TOPMODULE)_b_sim
+
+.PHONY: b_all
+b_all: b_compile  b_link    b_sim
+
+.PHONY: b_compile
+b_compile:
+	mkdir  -p build_b_sim
+	@echo Compiling for Bluesim ...
+	bsc -u -sim $(B_SIM_DIRS) $(BSC_COMP_FLAGS) $(BSC_PATHS) -g $(TOPMODULE)  $(TOPFILE) 
+	@echo Compiling for Bluesim finished
+
+.PHONY: b_link
+b_link:
+	@echo Linking for Bluesim ...
+	bsc -e $(TOPMODULE) -sim -o $(B_SIM_EXE) $(B_SIM_DIRS) $(BSC_LINK_FLAGS) $(BSC_PATHS)
+	@echo Linking for Bluesim finished
+
+.PHONY: b_sim
+b_sim:
+	@echo Bluesim simulation ...
+	./$(B_SIM_EXE)
+	@echo Bluesim simulation finished
+
+.PHONY: b_sim_vcd
+b_sim_vcd:
+	@echo Bluesim simulation and dumping VCD in dump.vcd ...
+	./$(B_SIM_EXE)  -V
+	@echo Bluesim simulation and dumping VCD in dump.vcd finished
+
+# ----------------------------------------------------------------
+# Verilog compile/link/sim
+
+V_DIRS = -vdir verilog_RTL -bdir build_v -info-dir build_v
+V_SIM_EXE = $(TOPMODULE)_v_sim
+V_COMP_FLAGS = -remove-dollar
+
+.PHONY: v_all
+v_all: v_compile  v_link  v_sim
+
+.PHONY: v_compile
+v_compile:
+	mkdir  -p build_v
+	mkdir  -p verilog_RTL
+	@echo Compiling for Verilog ...
+	bsc -u -verilog $(V_DIRS) $(BSC_COMP_FLAGS) $(BSC_PATHS) -g $(TOPMODULE)  $(TOPFILE)
+	@echo Compiling for Verilog finished
+
+.PHONY: v_link
+v_link:
+	@echo Linking for Verilog sim ...
+	bsc -e $(TOPMODULE) -verilog -o ./$(V_SIM_EXE) $(V_DIRS) -vsim $(V_SIM)  verilog_RTL/$(TOPMODULE).v
+	@echo Linking for Verilog sim finished
+
+.PHONY: v_sim
+v_sim:
+	@echo Verilog simulation...
+	./$(V_SIM_EXE)
+	@echo Verilog simulation finished
+
+.PHONY: v_sim_vcd
+v_sim_vcd:
+	@echo Verilog simulation and dumping VCD in dump.vcd ...
+	./$(V_SIM_EXE)  +bscvcd
+	@echo Verilog simulation and dumping VCD in dump.vcd finished
+
+# ----------------------------------------------------------------
+
+.PHONY: clean
+clean:
+	rm -rf  *.vcd build_v obj_dir* verilog_RTL *.so *_b_sim *_v_sim *.log

README.md

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+The humble beginnings of a UART loopback.
+
+``TOPMODULE=mkTop make v_compile`` to generate verilog. The generated verilog can
+be found in the ``verilog_RTL/`` folder.
+
+# Dependencies
+You'll need to install:
+1. [Yosys](https://github.com/YosysHQ/yosys) at git commit: 7ce5011c24b
+2. [nextpnr-0.4-36-gc8406b71](https://github.com/YosysHQ/nextpnr)
+3. [PrjTrellis](https://github.com/YosysHQ/prjtrellis) at git commit: 1.2.1-22-g35f5aff
+4. [openFPGALoader](https://github.com/trabucayre/openFPGALoader)
+
+# Programming the ULX3S
+Change into the folder containing this README, and then run ``
+
+```bash
+make -C ulx3s_fpga
+# You may need the following line to set your screen device config
+# to one parity and one stop bit. Tested working on MacOS, should
+# work on Linux.
+stty -f /dev/tty.usbserial-K00027 -cstopb -parenb
+screen /dev/tty.usbserial-K00027 9600
+```
+
+# Simulation
+TODO
+
+# Generating Verilog
+
+```bash
+TOPMODULE=mkTop make v_compile
+```

src/ClkDivider.bs

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+package ClkDivider(mkClkDivider, ClkDivider(..)) where
+
+interface (ClkDivider :: # -> *) hi =
+  {
+  reset :: Action
+  ;isAdvancing :: Bool
+  ;isHalfCycle :: Bool
+  }
+
+mkClkDivider :: Handle -> Module (ClkDivider hi)
+mkClkDivider fileHandle = do
+    counter <- mkReg(0 :: UInt (TLog hi))   
+    let hi_value :: UInt (TLog hi) = (fromInteger $ valueOf hi)
+    let half_hi_value :: UInt (TLog hi) = (fromInteger $ valueOf (TDiv hi 2))
+
+    let val :: Real = (fromInteger $ valueOf hi)
+    let msg = "Clock Div Period : " + (realToString val) + "\n"
+
+    hPutStr fileHandle msg
+    hPutStr fileHandle genModuleName
+
+    addRules $
+      rules
+        {-# ASSERT fire when enabled #-}
+        {-# ASSERT no implicit conditions #-}
+        "tick" : when True ==> action
+          $display (counter)
+          counter := if (counter == hi_value)
+                    then 0
+                    else counter + 1
+    
+    return $
+      interface ClkDivider
+        reset :: Action
+        reset = do
+          counter := 0
+
+        isAdvancing :: Bool
+        isAdvancing = (counter == hi_value)
+        isHalfCycle = (counter == half_hi_value)

src/Deserializer.bs

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+package Deserializer(
+  mkDeserialize,
+  IDeserializer(..),
+  State(..)) 
+  where
+
+import ClkDivider
+import State
+
+
+interface (IDeserializer :: # -> # -> *) clkFreq baudRate = 
+  get         ::  Bit 8            
+  putBitIn    :: (Bit 1) -> Action {-# always_enabled, always_ready #-}
+
+mkDeserialize :: Handle -> Module (IDeserializer clkFreq baudRate)
+mkDeserialize fileHandle = do
+  ftdiRxIn :: Wire(Bit 1) <- mkBypassWire
+  shiftReg :: Reg(Bit 8) <- mkReg(0)
+  ftdiState <- mkReg(IDLE)
+
+  clkDivider :: (ClkDivider (TDiv clkFreq baudRate)) <- mkClkDivider fileHandle
+
+  addRules $
+    rules
+
+      {-# ASSERT fire when enabled #-}
+      "IDLE" : when (ftdiState == IDLE), (ftdiRxIn == 0) ==>
+        do
+          clkDivider.reset
+          ftdiState := ftdiState' ftdiState
+
+      {-# ASSERT fire when enabled #-}
+      "NOT IDLE" : when (ftdiState /= IDLE), (clkDivider.isAdvancing) ==>
+        do
+          ftdiState := ftdiState' ftdiState
+
+      {-# ASSERT fire when enabled #-}
+        "SAMPLING" : when 
+          DATA(n) <- ftdiState,
+          n >= 0,
+          n <= 7, 
+          let sampleTrigger = clkDivider.isHalfCycle
+            in sampleTrigger
+          ==>
+            do
+              shiftReg := ftdiRxIn ++ shiftReg[7:1]
+
+  return $
+    interface IDeserializer
+    {get      = shiftReg when (ftdiState == STOP), (clkDivider.isAdvancing)
+    ;putBitIn bit = 
+      ftdiRxIn := bit
+    }

src/Serializer.bs

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+package Serializer(
+  mkSerialize,
+  ISerializer(..),
+  State(..)) 
+  where
+
+import ClkDivider
+import State
+
+serialize :: State -> Bit 8 -> Bit 1
+serialize ftdiState dataReg =
+    case ftdiState of
+        START    -> 1'b0
+        (DATA n) -> dataReg[n:n]
+        _        -> 1'b1
+
+interface (ISerializer :: # -> # -> *) clkFreq baudRate = 
+  putBit8    :: (Bit 8) -> Action {-# always_enabled, always_ready #-}
+  bitLineOut ::  Bit 1            {-# always_ready #-}
+
+mkSerialize :: Handle -> Module (ISerializer clkFreq baudRate)
+mkSerialize fileHandle = do
+
+  ftdiTxOut :: Wire(Bit 1) <- mkBypassWire
+  dataReg  :: Reg(Bit 8) <- mkReg(0)
+  ftdiState <- mkReg(IDLE)
+  clkDivider :: (ClkDivider (TDiv clkFreq baudRate)) <- mkClkDivider fileHandle
+
+  addRules $
+    rules
+      {-# ASSERT fire when enabled #-}
+      "ADVANCE UART STATE WHEN NOT IDLE" : when 
+        (ftdiState /= IDLE), 
+        (clkDivider.isAdvancing) ==>
+        do
+          ftdiState := ftdiState' ftdiState
+
+      {-# ASSERT fire when enabled #-}
+      "BIT LINE" : when True ==>
+        do
+          ftdiTxOut := serialize ftdiState dataReg
+
+  return $
+    interface ISerializer
+      putBit8  bit8Val = 
+        do
+          clkDivider.reset
+          dataReg := bit8Val 
+          ftdiState := ftdiState' ftdiState
+        when (ftdiState == IDLE)
+      bitLineOut = ftdiTxOut
+    

src/State.bs

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+package State(
+  State(..),
+  ftdiState') where
+
+data State = IDLE 
+           | START 
+           | DATA (UInt (TLog 8)) 
+           | PARITY 
+           | STOP
+           deriving (Bits, Eq, FShow)
+
+ftdiState' :: State -> State
+ftdiState' state = 
+  case state of
+    IDLE    -> START
+    START   -> DATA(0)
+    DATA(7) -> PARITY
+    DATA(n) -> DATA(n+1)
+    PARITY  -> STOP
+    STOP    -> IDLE

src/Top.bs

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+-- TOPMODULE=mkTop make b_compile
+package Top(mkTop, ITop(..), mkSim) where
+
+import Deserializer
+import Serializer
+
+type FCLK = 25_000_000
+type BAUD = 9_600
+
+interface ITop = 
+  ftdi_rxd    ::  Bit 1            {-# always_ready #-}
+  led         ::  Bit 8            {-# always_ready #-}
+  ftdi_txd    :: (Bit 1) -> Action {-# always_enabled, always_ready #-}
+
+{-# properties mkTop={verilog} #-}
+mkTop :: Module (ITop)
+mkTop = do
+
+  fileHandle <- openFile "compile.log" WriteMode 
+
+  deserializer :: (IDeserializer FCLK BAUD) <- mkDeserialize fileHandle
+  serializer :: (ISerializer FCLK BAUD) <- mkSerialize fileHandle
+  ftdiBitIn  :: Wire(Bit 1)       <- mkBypassWire
+  rxReg      :: Reg(Bit 8) <- mkReg(0)
+  messageM $ "Hallo!!" + (realToString 5)
+
+  addRules $
+    rules
+      when True ==>
+        do
+          rxReg := deserializer.get
+          serializer.putBit8 $ deserializer.get
+      
+      when True ==>
+        deserializer.putBitIn ftdiBitIn
+
+  return $
+    interface ITop
+    {ftdi_rxd = serializer.bitLineOut
+    ;led = rxReg
+    ;ftdi_txd bitIn = ftdiBitIn := bitIn}
+
+mkSim :: Module Empty
+mkSim = do
+  -- count :: Reg(UInt 3) <- mkReg(0)
+  count :: Reg(UInt 3) <- mkReg(0)
+  addRules $
+    rules
+      "count" : when True ==> action
+        count := unpack ((1'b1) ++ (pack count)[2:1])
+        $display count
+      "end sim" : when (count == 6) ==> action
+        $finish
+
+  return $
+    interface Empty

ulx3s_fpga/makefile

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+BSV_PATH=$(shell dirname $(shell which bsc))/..
+BSV_LIBS=$(BSV_PATH)/lib/Verilog
+TOPMODULE=mkTop
+IDCODE ?= 0x41113043 # 85f
+
+all: prog
+
+../verilog_RTL/$(TOPMODULE).v: ../src/Top.bs
+	V_SIM=verilator TOPMODULE=$(TOPMODULE) make -C ../ v_compile
+
+$(TOPMODULE).json: ../verilog_RTL/$(TOPMODULE).v
+	yosys \
+		-p "synth_ecp5 -top $(TOPMODULE) -json $@" \
+		-E $(TOPMODULE).d \
+		$< \
+		$(BSV_LIBS)/Counter.v
+
+$(TOPMODULE).config: $(TOPMODULE).json
+	nextpnr-ecp5 \
+		--json $< \
+		--textcfg $@ \
+		--lpf ulx3s_v20.lpf \
+		--85k \
+		--package CABGA381
+
+$(TOPMODULE).bit: $(TOPMODULE).config
+	ecppack --idcode $(IDCODE) $< $@
+
+.PHONY: prog
+prog: $(TOPMODULE).bit
+	openFPGALoader -f -b ulx3s $<
+
+.PHONY: clean
+clean:
+	rm -rf *.json *.config *.bit *.d
+	make -C ../ clean

ulx3s_fpga/ulx3s_v20.lpf

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+## ULX3S v2.x.x and v3.0.x
+
+# The clock "usb" and "gpdi" sheet
+LOCATE COMP "CLK" SITE "G2";
+IOBUF PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
+FREQUENCY PORT "CLK" 25 MHZ;
+
+# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash
+# write to FLASH possible any time from JTAG:
+#SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
+# write to FLASH possible from user bitstream:
+SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=DISABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
+
+## USBSERIAL FTDI-FPGA serial port "usb" sheet
+LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi
+LOCATE COMP "ftdi_txd_1" SITE "M1"; # FPGA receives from ftdi
+LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives
+LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives
+LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives
+IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33;
+IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33;
+IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33;
+IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33;
+
+## LED indicators "blinkey" and "gpio" sheet
+LOCATE COMP "led[7]" SITE "H3";
+LOCATE COMP "led[6]" SITE "E1";
+LOCATE COMP "led[5]" SITE "E2";
+LOCATE COMP "led[4]" SITE "D1";
+LOCATE COMP "led[3]" SITE "D2";
+LOCATE COMP "led[2]" SITE "C1";
+LOCATE COMP "led[1]" SITE "C2";
+LOCATE COMP "led[0]" SITE "B2";
+IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet
+LOCATE COMP "RST_N" SITE "D6";  # BTN_PWRn (inverted logic)
+LOCATE COMP "btn_1[0]" SITE "R1";  # FIRE1
+LOCATE COMP "btn_1[1]" SITE "T1";  # FIRE2
+LOCATE COMP "btn_1[2]" SITE "R18"; # UP
+LOCATE COMP "btn_1[3]" SITE "V1";  # DOWN
+LOCATE COMP "btn_1[4]" SITE "U1";  # LEFT
+LOCATE COMP "btn_1[5]" SITE "H16"; # RIGHT
+IOBUF PORT "RST_N" PULLMODE=UP IO_TYPE=LVCMOS33;
+IOBUF PORT "btn_1[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
+IOBUF PORT "btn_1[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
+IOBUF PORT "btn_1[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
+IOBUF PORT "btn_1[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
+IOBUF PORT "btn_1[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
+IOBUF PORT "btn_1[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
+
+## DIP switch "blinkey", "gpio" sheet
+LOCATE COMP "sw[0]" SITE "E8"; # SW1
+LOCATE COMP "sw[1]" SITE "D8"; # SW2
+LOCATE COMP "sw[2]" SITE "D7"; # SW3
+LOCATE COMP "sw[3]" SITE "E7"; # SW4
+IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
+IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
+IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
+IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
+
+## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet
+LOCATE COMP "oled_clk" SITE "P4";
+LOCATE COMP "oled_mosi" SITE "P3";
+LOCATE COMP "oled_dc" SITE "P1";
+LOCATE COMP "oled_resn" SITE "P2";
+LOCATE COMP "oled_csn" SITE "N2";
+IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## SPI Flash chip "flash" sheet
+LOCATE COMP "flash_csn" SITE "R2";
+#LOCATE COMP "flash_clk" SITE "U3";
+LOCATE COMP "flash_mosi" SITE "W2";
+LOCATE COMP "flash_miso" SITE "V2";
+LOCATE COMP "flash_holdn" SITE "W1";
+LOCATE COMP "flash_wpn" SITE "Y2";
+#LOCATE COMP "flash_csspin" SITE "AJ3";
+#LOCATE COMP "flash_initn" SITE "AG4";
+#LOCATE COMP "flash_done" SITE "AJ4";
+#LOCATE COMP "flash_programn" SITE "AH4";
+#LOCATE COMP "flash_cfg_select[0]" SITE "AM4";
+#LOCATE COMP "flash_cfg_select[1]" SITE "AL4";
+#LOCATE COMP "flash_cfg_select[2]" SITE "AK4";
+IOBUF PORT "flash_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "flash_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "flash_mosi" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "flash_miso" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "flash_holdn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "flash_wpn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
+
+## SD card "sdcard", "usb" sheet
+LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14
+LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15
+LOCATE COMP "sd_d[0]" SITE "J3"; # sd_dat0_do (MISO) WiFi GPIO2
+LOCATE COMP "sd_d[1]" SITE "H1"; # sd_dat1_irq WiFi GPIO4
+LOCATE COMP "sd_d[2]" SITE "K1"; # sd_dat2 WiFi_GPIO12
+LOCATE COMP "sd_d[3]" SITE "K2"; # sd_dat3_csn WiFi_GPIO13
+LOCATE COMP "sd_wp" SITE "P5"; # not connected
+LOCATE COMP "sd_cdn" SITE "N5"; # not connected
+IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sd_d[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement
+IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## ADC SPI (MAX11123) "analog", "ram" sheet
+LOCATE COMP "adc_csn" SITE "R17";
+LOCATE COMP "adc_mosi" SITE "R16";
+LOCATE COMP "adc_miso" SITE "U16";
+LOCATE COMP "adc_sclk" SITE "P17";
+IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## Audio 4-bit DAC "analog", "gpio" sheet
+# Output impedance 75 ohm.
+# Strong enough to drive 16 ohm earphones.
+LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio)
+LOCATE COMP "audio_l[2]" SITE "C3";
+LOCATE COMP "audio_l[1]" SITE "D3";
+LOCATE COMP "audio_l[0]" SITE "E4";
+LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio)
+LOCATE COMP "audio_r[2]" SITE "D5";
+LOCATE COMP "audio_r[1]" SITE "B5";
+LOCATE COMP "audio_r[0]" SITE "A3";
+LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio)
+LOCATE COMP "audio_v[2]" SITE "F5";
+LOCATE COMP "audio_v[1]" SITE "F2";
+LOCATE COMP "audio_v[0]" SITE "H5";
+IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+
+## WiFi ESP-32 "wifi", "usb", "flash" sheet
+# other pins are shared with GP/GN, SD card and JTAG
+LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi
+LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi
+LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi
+LOCATE COMP "wifi_gpio0" SITE "L2";
+LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED
+LOCATE COMP "wifi_gpio16" SITE "L1"; # Serial1 RX
+LOCATE COMP "wifi_gpio17" SITE "N3"; # Serial1 TX
+# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active
+IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "wifi_gpio5" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## PCB antenna 433 MHz (may be also used for FM) "usb" sheet
+LOCATE COMP "ant_433mhz" SITE "G1";
+IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+## Second USB port "US2" going directly into FPGA "usb", "ram" sheet
+LOCATE COMP "usb_fpga_dp" SITE "E16"; # single ended or differential input only
+LOCATE COMP "usb_fpga_dn" SITE "F16";
+IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16;
+IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16;
+LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # single-ended bidirectional
+LOCATE COMP "usb_fpga_bd_dn" SITE "E15";
+IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+LOCATE COMP "usb_fpga_pu_dp" SITE "B12"; # pull up/down control
+LOCATE COMP "usb_fpga_pu_dn" SITE "C12";
+IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+IOBUF PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
+
+## JTAG ESP-32 "usb" sheet
+# connected to FT231X and ESP-32
+# commented out because those are dedicated pins, not directly useable as GPIO
+# but could be used by some vendor-specific JTAG bridging (boundary scan) module
+#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI   FPGA receives
+#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS  FPGA transmits
+#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR  FPGA receives
+#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD  FPGA receives
+#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## SDRAM "ram" sheet
+LOCATE COMP "sdram_clk" SITE "F19";
+LOCATE COMP "sdram_cke" SITE "F20";
+LOCATE COMP "sdram_csn" SITE "P20";
+LOCATE COMP "sdram_wen" SITE "T20";
+LOCATE COMP "sdram_rasn" SITE "R20";
+LOCATE COMP "sdram_casn" SITE "T19";
+LOCATE COMP "sdram_a[0]" SITE "M20";
+LOCATE COMP "sdram_a[1]" SITE "M19";
+LOCATE COMP "sdram_a[2]" SITE "L20";
+LOCATE COMP "sdram_a[3]" SITE "L19";
+LOCATE COMP "sdram_a[4]" SITE "K20";
+LOCATE COMP "sdram_a[5]" SITE "K19";
+LOCATE COMP "sdram_a[6]" SITE "K18";
+LOCATE COMP "sdram_a[7]" SITE "J20";
+LOCATE COMP "sdram_a[8]" SITE "J19";
+LOCATE COMP "sdram_a[9]" SITE "H20";
+LOCATE COMP "sdram_a[10]" SITE "N19";
+LOCATE COMP "sdram_a[11]" SITE "G20";
+LOCATE COMP "sdram_a[12]" SITE "G19";
+LOCATE COMP "sdram_ba[0]" SITE "P19";
+LOCATE COMP "sdram_ba[1]" SITE "N20";
+LOCATE COMP "sdram_dqm[0]" SITE "U19";
+LOCATE COMP "sdram_dqm[1]" SITE "E20";
+LOCATE COMP "sdram_d[0]" SITE "J16";
+LOCATE COMP "sdram_d[1]" SITE "L18";
+LOCATE COMP "sdram_d[2]" SITE "M18";
+LOCATE COMP "sdram_d[3]" SITE "N18";
+LOCATE COMP "sdram_d[4]" SITE "P18";
+LOCATE COMP "sdram_d[5]" SITE "T18";
+LOCATE COMP "sdram_d[6]" SITE "T17";
+LOCATE COMP "sdram_d[7]" SITE "U20";
+LOCATE COMP "sdram_d[8]" SITE "E19";
+LOCATE COMP "sdram_d[9]" SITE "D20";
+LOCATE COMP "sdram_d[10]" SITE "D19";
+LOCATE COMP "sdram_d[11]" SITE "C20";
+LOCATE COMP "sdram_d[12]" SITE "E18";
+LOCATE COMP "sdram_d[13]" SITE "F18";
+LOCATE COMP "sdram_d[14]" SITE "J18";
+LOCATE COMP "sdram_d[15]" SITE "J17";
+IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+# GPDI differential interface (Video) "gpdi" sheet
+LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue +
+LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue -
+LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green +
+LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green -
+LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red +
+LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Red -
+LOCATE COMP "gpdi_dp[3]" SITE "A17"; # Clock +
+LOCATE COMP "gpdi_dn[3]" SITE "B18"; # Clock -
+LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet +
+LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet -
+LOCATE COMP "gpdi_cec" SITE "A18";
+LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC
+LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12
+IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet
+# Physical connector pins:
+# *** when FEMALE ANGLED (90 deg PMOD) soldered ***
+# Jm_n- = Jm_n, Jm_n+ = Jm_n+1
+# example: J1_5- is J1_5 phsyical, J1_5+ is J1_6 physical
+# *** when MALE VERTICAL soldered ***
+# Jm_n+ = Jm_n, Jm_n- = Jm_n+1
+# example: J1_5+ is J1_5 physical, J1_5- is J1_6 physical
+# Pins enumerated gp[0-27], gn[0-27].
+# With differential mode enabled on Lattice,
+# gp[] (+) are used, gn[] (-) are ignored from design
+# as they handle inverted signal by default.
+# To enable differential, rename LVCMOS33->LVCMOS33D
+# To enable clock i/o, add this (example):
+#FREQUENCY PORT "gp[12]" 25.00 MHZ;
+LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
+LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
+LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
+LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK
+LOCATE COMP "gp[2]" SITE "A9";  # J1_9+  GP2 GR_PCLK
+LOCATE COMP "gn[2]" SITE "B10"; # J1_9-  GN2 GR_PCLK
+LOCATE COMP "gp[3]" SITE "B9";  # J1_11+ GP3
+LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3
+LOCATE COMP "gp[4]" SITE "A7";  # J1_13+ GP4
+LOCATE COMP "gn[4]" SITE "A8";  # J1_13- GN4
+LOCATE COMP "gp[5]" SITE "C8";  # J1_15+ GP5
+LOCATE COMP "gn[5]" SITE "B8";  # J1_15- GN5
+LOCATE COMP "gp[6]" SITE "C6";  # J1_17+ GP6
+LOCATE COMP "gn[6]" SITE "C7";  # J1_17- GN6
+IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+LOCATE COMP "gp[7]" SITE "A6";  # J1_23+ GP7
+LOCATE COMP "gn[7]" SITE "B6";  # J1_23- GN7
+LOCATE COMP "gp[8]" SITE "A4";  # J1_25+ GP8
+LOCATE COMP "gn[8]" SITE "A5";  # J1_25- GN8  DIFF
+LOCATE COMP "gp[9]" SITE "A2";  # J1_27+ GP9  DIFF
+LOCATE COMP "gn[9]" SITE "B1";  # J1_27- GN9  DIFF
+LOCATE COMP "gp[10]" SITE "C4";  # J1_29+ GP10 DIFF
+LOCATE COMP "gn[10]" SITE "B4";  # J1_29- GN10 DIFF
+LOCATE COMP "gp[11]" SITE "F4";  # J1_31+ GP11 DIFF WIFI_GPIO26
+LOCATE COMP "gn[11]" SITE "E3";  # J1_31- GN11 DIFF WIFI_GPIO25
+LOCATE COMP "gp[12]" SITE "G3";  # J1_33+ GP12 DIFF WIFI_GPIO33 PCLK
+LOCATE COMP "gn[12]" SITE "F3";  # J1_33- GN12 DIFF WIFI_GPIO32 PCLK
+LOCATE COMP "gp[13]" SITE "H4";  # J1_35+ GP13 DIFF WIFI_GPIO35
+LOCATE COMP "gn[13]" SITE "G5";  # J1_35- GN13 DIFF WIFI_GPIO34
+IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+LOCATE COMP "gp[14]" SITE "U18"; # J2_5+  GP14 DIFF ADC1
+LOCATE COMP "gn[14]" SITE "U17"; # J2_5-  GN14 DIFF ADC0
+LOCATE COMP "gp[15]" SITE "N17"; # J2_7+  GP15 DIFF ADC3
+LOCATE COMP "gn[15]" SITE "P16"; # J2_7-  GN15 DIFF ADC2
+LOCATE COMP "gp[16]" SITE "N16"; # J2_9+  GP16 DIFF ADC5
+LOCATE COMP "gn[16]" SITE "M17"; # J2_9-  GN16 DIFF ADC4
+LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 DIFF ADC7 GR_PCLK
+LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 DIFF ADC6
+LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 DIFF
+LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 DIFF
+LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 DIFF
+LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 DIFF
+LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 DIFF
+LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 DIFF
+IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 DIFF
+LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 DIFF
+LOCATE COMP "gp[22]" SITE "B15"; # J2_25+ GP22
+LOCATE COMP "gn[22]" SITE "C15"; # J2_25- GN22
+LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23
+LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23
+LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24
+LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24
+LOCATE COMP "gp[25]" SITE "D14"; # J2_31+ GP25
+LOCATE COMP "gn[25]" SITE "E14"; # J2_31- GN25
+LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26
+LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26
+LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27
+LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27
+IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## PROGRAMN (reload bitstream from FLASH, exit from bootloader)
+# PCB v2.0.5 and higher
+LOCATE COMP "user_programn" SITE "M4";
+IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5)
+# on PCB v1.7 shutdown is not connected to FPGA
+LOCATE COMP "shutdown" SITE "G16"; # FPGA receives
+IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;