173 lines
5 KiB
Makefile
173 lines
5 KiB
Makefile
### -*-Makefile-*-
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# Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved.
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# ================================================================
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# This is an example Makefile for the examples in this tutorial
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# You should only have to edit the variable definitions in the
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# following section (or override them from the 'make' command line)
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# Your PATH should include the directory where your 'bsc' binary lives
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# For example, if you cloned:
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# https://github.com/B-Lang-org/bsc
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# into
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# ~/git_clones/bsc
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# and built 'bsc' there using the standard 'make all', you'd add
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# ~/git_clones/bsc/inst/bin
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# to your PATH
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#
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# Do 'bsc -v' or 'bsc -help' to test that you can invoke bsc.
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# ================================================================
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# Please modify the following for your installation and setup
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# Directory containing this tutorial
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TUTORIAL ?= ..
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# Set this to the command that invokes your Verilog simulator
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# V_SIM ?= verilator
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# V_SIM ?= iverilog
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# V_SIM ?= cvc
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# V_SIM ?= cver
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# V_SIM ?= vcsi
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# V_SIM ?= vcs
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# V_SIM ?= modelsim
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# V_SIM ?= ncsim
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# V_SIM ?= ncverilog
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ifeq ($(V_SIM),verilator)
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V_SIM += -Xv --no-timing
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endif
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# ================================================================
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# You should not have to change anything below this line
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RESOURCES_DIR ?= $(TUTORIAL)/Resources
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TOPLANG ?= BH
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ifeq ($(TOPLANG),BSV)
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SRC_EXT=bsv
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else ifeq ($(TOPLANG),BH)
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SRC_EXT=bs
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else
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SRC_EXT=TOPLANG_NOT_DEFINED
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endif
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TOPFILE ?= src/Top.$(SRC_EXT)
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TOPMODULE ?= mkTop
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BSC_COMP_FLAGS += \
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-keep-fires \
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-aggressive-conditions \
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-no-warn-action-shadowing \
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-check-assert \
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-cpp \
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-show-schedule \
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+RTS -K128M -RTS -show-range-conflict \
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$(BSC_COMP_FLAG1) $(BSC_COMP_FLAG2) $(BSC_COMP_FLAG3)
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BSC_LINK_FLAGS += -keep-fires
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BSC_PATHS = -p src/:+
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.PHONY: help
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help:
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@echo ""
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@echo "Targets for 'make':"
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@echo " help Print this information"
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@echo ""
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@echo " Bluesim:"
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@echo " b_compile Compile for Bluesim"
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@echo " b_link Link a Bluesim executable"
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@echo " b_sim Run the Bluesim simulation executable"
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@echo " b_all Convenience for 'make b_compile b_link b_sim'"
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@echo " b_sim_vcd Run the Bluesim simulation executable and generate VCD"
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@echo ""
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@echo " Verilog generation and Verilog sim:"
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@echo " v_compile Compile for Verilog (Verilog files generated in verilog_RTL/)"
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@echo " v_link Link a Verilog simulation executable"
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@echo " (current simulator:" $(V_SIM) " (redefine V_SIM for other Verilog simulators)"
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@echo " v_sim Run the Verilog simulation executable"
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@echo " v_all Convenience for 'make v_compile v_link v_sim'"
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@echo " v_sim_vcd Run the Verilog simulation executable and dump VCD"
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@echo ""
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@echo " clean Delete intermediate files in build_b_sim/ and build_v/ dirs"
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@echo " full_clean Delete all but this Makefile"
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# ================================================================
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# Bluesim compile/link/simulate
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B_SIM_DIRS = -simdir build_b_sim -bdir build_b_sim -info-dir build_b_sim
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B_SIM_EXE = $(TOPMODULE)_b_sim
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.PHONY: b_all
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b_all: b_compile b_link b_sim
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.PHONY: b_compile
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b_compile:
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mkdir -p build_b_sim
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@echo Compiling for Bluesim ...
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bsc -u -sim $(B_SIM_DIRS) $(BSC_COMP_FLAGS) $(BSC_PATHS) -g $(TOPMODULE) $(TOPFILE)
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@echo Compiling for Bluesim finished
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.PHONY: b_link
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b_link:
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@echo Linking for Bluesim ...
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bsc -e $(TOPMODULE) -sim -o $(B_SIM_EXE) $(B_SIM_DIRS) $(BSC_LINK_FLAGS) $(BSC_PATHS)
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@echo Linking for Bluesim finished
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.PHONY: b_sim
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b_sim:
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@echo Bluesim simulation ...
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./$(B_SIM_EXE)
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@echo Bluesim simulation finished
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.PHONY: b_sim_vcd
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b_sim_vcd:
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@echo Bluesim simulation and dumping VCD in dump.vcd ...
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./$(B_SIM_EXE) -V
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@echo Bluesim simulation and dumping VCD in dump.vcd finished
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# ----------------------------------------------------------------
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# Verilog compile/link/sim
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V_DIRS = -vdir verilog_RTL -bdir build_v -info-dir build_v
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V_SIM_EXE = $(TOPMODULE)_v_sim
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V_COMP_FLAGS = -remove-dollar
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.PHONY: v_all
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v_all: v_compile v_link v_sim
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.PHONY: v_compile
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v_compile:
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mkdir -p build_v
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mkdir -p verilog_RTL
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@echo Compiling for Verilog ...
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bsc -u -verilog $(V_DIRS) $(BSC_COMP_FLAGS) $(BSC_PATHS) -g $(TOPMODULE) $(TOPFILE)
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@echo Compiling for Verilog finished
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.PHONY: v_link
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v_link:
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@echo Linking for Verilog sim ...
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bsc -e $(TOPMODULE) -verilog -o ./$(V_SIM_EXE) $(V_DIRS) -vsim $(V_SIM) verilog_RTL/$(TOPMODULE).v
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@echo Linking for Verilog sim finished
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.PHONY: v_sim
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v_sim:
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@echo Verilog simulation...
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./$(V_SIM_EXE)
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@echo Verilog simulation finished
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.PHONY: v_sim_vcd
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v_sim_vcd:
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@echo Verilog simulation and dumping VCD in dump.vcd ...
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./$(V_SIM_EXE) +bscvcd
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@echo Verilog simulation and dumping VCD in dump.vcd finished
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# ----------------------------------------------------------------
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.PHONY: clean
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clean:
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rm -rf *.vcd build_v obj_dir* verilog_RTL *.so *_b_sim *_v_sim *.log
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