79 lines
3.4 KiB
Markdown
79 lines
3.4 KiB
Markdown
# What is it?
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Haskellator is an experimental tool designed to unlock new possibilities in processing RTL (Register-Transfer Level) netlists. It aims to enhance simulation efficiency, offer insightful change analysis, and explore experimental synthesis techniques.
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### Key Features:
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- **Sparse Simulation**:
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Traditional open-source RTL simulators store signal values every time a signal changes.
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HaskellatorSim will save signal states only if they’ve changed
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within the last host CPU second of simulation. This approach compresses the simulation
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data whilst enabling quick recomputation of any gaps when viewing saved simulations.
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This requires access to the RTLIL sources and simulation save files to fill in any gaps.
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- **Change Condition Analysis**:
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Haskellator will provide tools to analyze and trace the cause of signal changes during
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simulation. By forming hypotheses about which signals influenced a change, it offers a
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"git-blame" style feature for simulations. This functionality also requires access to
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the original RTLIL sources and simulation save files.
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- **Experimental Synthesis Techniques**:
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We hope to explore the potential of using reinforcement learning neural networks to
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optimize synthesis passes for input netlists. The synthesized netlist could be placed
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and routed to determine fmax, which could be used as the score the neural network will
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learn to optimize.
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These are just a few of the concepts we're experimenting with. The broader goal is to
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explore innovative ideas, develop a high-quality tool that can evolve with community
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input, and just have fun!
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# Status
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Right now Haskellator can successfully parse some valid RTLIL into [an AST](./src/RTLIL/Syntax.hs).
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We are currently working on expanding the RTLIL that can be parsed to include
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[RTLIL](https://github.com/YosysHQ/yosys/blob/main/kernel/rtlil.h)
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emitted from Amaranth Lang.
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Currently targetting RTLIL in Yosys .47.
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# Usage
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## Run and Build With Nix(Linux and MacOS)
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The following will allow you to see a pretty printed
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AST for the given input `il` file.
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```bash
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git clone --recursive git@github.com:JoyOfHardware/Haskellator.git
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$ nix-shell
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$ rtlil-parse
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```
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# TODO
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- [ ] automated CICD on gitea on personal servers
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- [ ] update to have support for four state logic by converting 'X' and 'Z' to zero
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- [ ] validation pass that checks that `ConstantInteger Int` is
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32 bits, that is, within range \[-2147483648, 2147483648)
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- [ ] Reverse/repair cell-stmt
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# Limitations
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- Does not support propagating non-two state logic, that is, no
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support for X or Z values. Default behavior is to reject such
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input although future iterations may support initializing X and
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Z to 0.
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- All cycles in circuit graphs must have at one D Flip-Flop on the
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cycle path. This requirement necesarily pre-cludes simulation of
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circuits such as NAND level-resolution SRAMs. The main reason for
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this restriction is to avoid having to handle metastability in
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simulation.
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I have yet to evaluate the implications of how this affects
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multi-clock domain circuits and their associated primitives such
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as asynchronous FIFOs, but I plan to make sure simulation of such
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circuits is possible and correct.
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# Lessons Learned
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- Should have written parser to be token based where after consuming
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and capturing token, we consume and discard all following whitespaces
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as well as comments... |