57 lines
2.3 KiB
Markdown
57 lines
2.3 KiB
Markdown
# General and Planning
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- [ ] might need many validation phases
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- [ ] it's conceivable that one could construct a Yosys memory Cell
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with invalid parameters
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- [ ] detect mismatched sizes in assignments
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- [ ] need canonical form making it easy to run all these validation
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passes
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- [ ] are recursive slices inclusive?
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- [ ] what are the semantics of connection `<conn-stmt>`? Where is
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`<conn-stmt>` employed?
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- [ ] Validate that `123456789[0:9][0:8]` is valid RTLIL
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- [ ] add validation section to README
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- [ ] just support Cell memV2
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- [ ] for value, what happens if we have 0 binary digits
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- [ ] modify parser to ignore comments... - should probably wait until
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parser is finished before asking
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- [ ] modify AST to support src tracking - needed to allow for human
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readable and correctable validation errors
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- [ ] when writing simulator, must specify directions on cell ports
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- [ ] in the <process>, why are we allowed to have <assign-stmt> before
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and after the optional <switch> stmt?
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- [ ] inspect Chris's mini-RTLIL
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- [ ] add RST grammar file to repo
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- [ ] name parsers so that that we know where failures occured
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- [ ] may want to also derive equality statements
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- [x] replace both `pEol *> pMaybeWs` and `pEol <* pMaybeWs`
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with `pEolAndAdvanceToNextNonWs`
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- [ ] Check inline sequencing of whitespace parsers in do blocks.
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Terminating instances of `pWs` should be preceeded by `<*`
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# Parser Development
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- [x] Sync
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- [ ] Process
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- [ ] Module
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# Parser Verification
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- [ ] I think only EOL terminated parsers should be responsible
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for pre-winding the Parsec scanner to the next non-space...
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- [ ] lift grammar into prover and show that all EOL terminated parsers
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are either followed by EOF or a keyword such "module", "autoidx",
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etc
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- [ ] first, manually inspect switch parser and try and see if it
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can infinitely recurse... Then empirically validate against
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corpus
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# Simulation Behavior
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- [ ] Figure out the computational semantics of what it means to
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sync on `high`. I already understand the computational
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semantics around synchronizing on `posedge` for example...
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# Simulation
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- [ ] dump to VCD
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- [ ] Write dynamically typed executor in Haskell
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- [ ] Subsequent IR passes may emerge natrually
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# Optimizations
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- [ ] squeeze out recursive slices |