actively re-orging by section

atoms.txt

@@ -20,9 +20,9 @@
  - [x] <wire-stmt> ::= “wire” <wire-option>* <wire-id> <eol>
  - [x] <wire-id> ::= <id>
  - [x] <wire-option> ::= “width” <integer> | “offset” <integer> | “input” <integer> | “output” <integer> | “inout” <integer> | “upto” | “signed”
- - [ ] <memory> ::= <attr-stmt>* <memory-stmt>
+ - [x] <memory> ::= <attr-stmt>* <memory-stmt>
- - [ ] <memory-stmt> ::= “memory” <memory-option>* <id> <eol>
+ - [x] <memory-stmt> ::= “memory” <memory-option>* <id> <eol>
- - [ ] <memory-option> ::= “width” <integer> | “size” <integer> | “offset” <integer>
+ - [x] <memory-option> ::= “width” <integer> | “size” <integer> | “offset” <integer>
  - [ ] <cell> ::= <attr-stmt>* <cell-stmt> <cell-body-stmt>* <cell-end-stmt>
  - [ ] <cell-stmt> ::= "cell" <cell-id> <cell-type> <eol>
  - [x] <cell-id> ::= <id>

src/RTLILParser/AST.hs

@@ -12,20 +12,59 @@ import Text.Read (Lexeme(Ident))
 import Data.Functor.Contravariant (Contravariant)
 import GHC.RTS.Flags (DoCostCentres(CostCentresAll))
 
-data PublicId       = PublicId      String  deriving (Show)
+-- taken from: https://yosyshq.readthedocs.io/projects/yosys/en/0.47/appendix/rtlil_text.html
-data AutogenId      = AutogenId     String  deriving (Show)
+-- types below organized accordingly
-data Slice          = Slice         Int (Maybe Int) deriving (Show)
+
+-- identifiers
 data Id             = Public    PublicId
                     | Autogen   AutogenId
                     deriving (Show)
-data WireId         = WireId    Id deriving (Show)
+data PublicId       = PublicId      String  deriving (Show)
-data MemoryID       = MemoryID  Id deriving (Show)
+data AutogenId      = AutogenId     String  deriving (Show)
+
+-- values
+data Value = Value
+    { width :: Int
+    , value :: Int
+    }
+    deriving (Show)
+
+-- strings
+-- comments
+-- file
+
+-- Autoindex statements
 data AutoIdxStmt    = AutoIdxStmt   Int     deriving (Show)
+
+-- Module
+data ParamStmt = ParamStmt
+    { paramId       :: Id
+    , paramConstant :: Maybe Constant
+    }
+    deriving (Show)
+data Constant = ConstantValue   Value
+              | ConstantInteger Int
+              | ConstantString  String
+              deriving (Show)
+
+-- Attribute statements
 data AttrStmt       = AttrStmt      Id Constant deriving (Show)
-data CellStmt       = CellStmt      CellId CellType  deriving (Show)
+
-data CellId         = CellId        Id deriving (Show)
+-- Signal Specifications
-data CellType       = CellType      Id deriving (Show)
+data SigSpec        = SigSpecConstant   Constant
+                    | SigSpecWireId     WireId
+                    | SigSpecSlice      SigSpec Slice
+                    | SigSpecConcat     [SigSpec]
+                    deriving (Show)
+data Slice          = Slice         Int (Maybe Int) deriving (Show)
+
+-- Connections
 data ConnStmt       = ConnStmt      SigSpec SigSpec deriving (Show)
+
+-- Wires
+data Wire           = Wire          WireStmt [AttrStmt] deriving (Show)
+data WireStmt       = WireStmt      WireId [WireOption] deriving (Show)
+data WireId         = WireId    Id deriving (Show)
 data WireOption     = WireOptionWidth   Int
                     | WireOptionOffset  Int
                     | WireOptionInput   Int
@@ -34,30 +73,21 @@ data WireOption     = WireOptionWidth   Int
                     | WireOptionUpto
                     | WireOptionSigned
                     deriving (Show)
-data WireStmt       = WireStmt      WireId [WireOption] deriving (Show)
+
-data Wire           = Wire          WireStmt [AttrStmt] deriving (Show)
+-- Memories
+data Memory         = Memory        MemoryStmt [AttrStmt] deriving (Show)
+data MemoryID       = MemoryID  Id deriving (Show)
+data MemoryStmt     = MemoryStmt    MemoryID [MemoryOption] deriving (Show)
 data MemoryOption   = MemoryOptionWidth     Int
                     | MemoryOptionSize      Int
                     | MemoryOptionOffset    Int
                     deriving (Show)
-data MemoryStmt     = MemoryStmt    MemoryID [MemoryOption] deriving (Show)
+
-data Memory         = Memory        MemoryStmt [AttrStmt] deriving (Show)
+-- Cells
-data SigSpec        = SigSpecConstant   Constant
+data CellStmt       = CellStmt      CellId CellType  deriving (Show)
-                    | SigSpecWireId     WireId
+data CellId         = CellId        Id deriving (Show)
-                    | SigSpecSlice      SigSpec Slice
+data CellType       = CellType      Id deriving (Show)
-                    | SigSpecConcat     [SigSpec]
+
-                    deriving (Show)
+-- Processes
-data Value = Value
+-- Switches
-    { width :: Int
+-- Syncs
-    , value :: Int
-    }
-    deriving (Show)
-data Constant = ConstantValue   Value
-              | ConstantInteger Int
-              | ConstantString  String
-              deriving (Show)
-data ParamStmt = ParamStmt
-    { paramId       :: Id
-    , paramConstant :: Maybe Constant
-    }
-    deriving (Show)

src/RTLILParser/Parser.hs

@@ -1,8 +1,5 @@
--- this parser largely references:
--- https://yosyshq.readthedocs.io/projects/yosys/en/stable/appendix/rtlil_text.html
 module RTLILParser.Parser(a, val) where
 
-
 import Control.Monad (void)
 import Text.Parsec
 import Text.Parsec.String (Parser)
@@ -17,42 +14,74 @@ import RTLILParser.AST(
    ,MemoryID(..)
     )
 import Util(binaryStringToInt)
-import RTLILParser.Primitives(pEscapedChar)
+import RTLILParser.Primitives(
+    pWs
+   ,pNonWs
+   ,pMaybeWs
+   ,pEol
+   ,pOctal
+   ,pEscapedChar
+    )
 
--- https://github.com/YosysHQ/yosys/blob/111b747d2797238eadf541879848492a9d34909a/frontends/rtlil/rtlil_lexer.l#L88C1-L88C17
+-- taken from: https://yosyshq.readthedocs.io/projects/yosys/en/0.47/appendix/rtlil_text.html
-nonws :: Parser Char
+-- parsers below are split int sections from the above link
-nonws = noneOf " \t\r\n"
-
-pMaybeWs :: Parser String
-pMaybeWs = many (oneOf " \t")
-
-pWs :: Parser String
-pWs = many1 (oneOf " \t")
-
-pEol :: Parser String
-pEol = many1 (oneOf "\r\n")
-
-pPublicId   :: Parser PublicId
-pPublicId   = PublicId <$> (char '\\' *> many1 nonws)
-
-pAutogenId  :: Parser AutogenId
-pAutogenId  = AutogenId <$> (char '$' *> many1 nonws)
 
+-- identifiers
 pId :: Parser Id
 pId = Public  <$> pPublicId
   <|> Autogen <$> pAutogenId
 
-pWireId :: Parser WireId
+pPublicId   :: Parser PublicId
-pWireId = WireId <$> pId
+pPublicId   = PublicId <$> (char '\\' *> many1 pNonWs)
 
-decimalDigit :: Parser Char
+pAutogenId  :: Parser AutogenId
-decimalDigit = oneOf "0123456789"
+pAutogenId  = AutogenId <$> (char '$' *> many1 pNonWs)
+
+-- values
+pValue :: Parser Value
+pValue = do
+    width <- many1 pDecimalDigit
+    _ <- char '\''
+    value <- many pBinaryDigit
+    return $ Value (read width) (binaryStringToInt value)
+
+pDecimalDigit :: Parser Char
+pDecimalDigit = oneOf "0123456789"
 
 -- update in the future to support 4 state logic
 -- by converting x and z to 0 and warning about it.
 pBinaryDigit :: Parser Char
 pBinaryDigit = oneOf "01"
 
+pInteger :: Parser Int
+pInteger = do
+    sign <- optionMaybe (char '-')
+    digits <- many1 pDecimalDigit
+    let value = read digits
+    return $ case sign of
+        Just _  -> -value
+        Nothing ->  value
+
+-- strings
+-- comments
+-- file
+-- Autoindex statements
+-- Module
+-- Attribute statements
+-- Signal Specifications
+-- Connections
+-- Wires
+-- Memories
+-- Cells
+-- Processes
+-- Switches
+-- Syncs
+
+pWireId :: Parser WireId
+pWireId = WireId <$> pId
+
+
+
 pString :: Parser String
 pString =
     between delimiter delimiter parseString
@@ -60,20 +89,6 @@ pString =
         delimiter = char '"'
         parseString = many (pEscapedChar <|> noneOf "\\\"")
 
-
-pValue :: Parser Value
-pValue = Value  <$> pInteger
-                <*> (binaryStringToInt <$> many1 pBinaryDigit)
-
-pInteger :: Parser Int
-pInteger = do
-    sign <- optionMaybe (char '-')
-    digits <- many1 digit
-    let value = read digits
-    return $ case sign of
-        Just _  -> -value
-        Nothing ->  value
-
 pConstant :: Parser Constant
 pConstant =
     try (ConstantValue <$> pValue)
@@ -198,6 +213,14 @@ pMemory = do
     memoryStmt <- pMemoryStmt
     return $ Memory memoryStmt attrs
 
+-- <cell>              ::= <attr-stmt>* <cell-stmt> <cell-body-stmt>* <cell-end-stmt>
+-- <cell-stmt>         ::= cell <cell-type> <cell-id> <eol>
+-- <cell-id>           ::= <id>
+-- <cell-type>         ::= <id>
+-- <cell-body-stmt>    ::= parameter (signed | real)? <id> <constant> <eol>
+--                      |  connect <id> <sigspec> <eol>
+-- <cell-end-stmt>     ::= end <eol>
+
 -- would correspond to `123456789[0:9][0:8]`
 exampleSigSpecSlice = 
     SigSpecSlice 

src/RTLILParser/Primitives.hs

@@ -1,6 +1,10 @@
 module RTLILParser.Primitives(
-    pOctal,
+    pWs
-    pEscapedChar
+   ,pNonWs
+   ,pMaybeWs
+   ,pEol
+   ,pOctal
+   ,pEscapedChar
 ) where
 
 import Control.Monad (void)
@@ -9,7 +13,6 @@ import Text.Parsec.String (Parser)
 import Data.Char (digitToInt)
 import Util(binaryStringToInt, octalStringToInt)
 
-
 pOctal :: Parser Char
 pOctal = do
     digits <- count 1 digit -- At least 1 digit
@@ -26,4 +29,17 @@ pEscapedChar = do
         , char 't' >> return '\t'
         , try pOctal             
         , anyChar                
-        ]
+        ]
+
+pMaybeWs :: Parser String
+pMaybeWs = many (oneOf " \t")
+
+pWs :: Parser String
+pWs = many1 (oneOf " \t")
+
+-- https://github.com/YosysHQ/yosys/blob/111b747d2797238eadf541879848492a9d34909a/frontends/rtlil/rtlil_lexer.l#L88C1-L88C17
+pNonWs :: Parser Char
+pNonWs = noneOf " \t\r\n"
+
+pEol :: Parser String
+pEol = many1 (oneOf "\r\n")