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converted to bluespec haskell

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This commit is contained in:
Yehowshua Immanuel 2024-05-19 22:16:33 -04:00
parent 72788b8436
commit cf68a5e683
17 changed files with 342 additions and 339 deletions
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4
.gitignore vendored
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@ -12,6 +12,10 @@ build_b_sim
mkSim_b_sim
verilog_RTL
# files generated for FPGA ULX3s implementation
ulx3s_fpga/mkTop.d
ulx3s_fpga/mkTop.json
# generated experiment outputs
experiments/bram/*.cxx
experiments/bram/*.h

6
Makefile
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@ -33,7 +33,7 @@ BDPI_OBJ = bdpi/uart_sim_device.o
RESOURCES_DIR ?= $(TUTORIAL)/Resources
TOPLANG ?= BSV
TOPLANG ?= BH
ifeq ($(TOPLANG),BSV)
SRC_EXT=bsv
@ -43,7 +43,7 @@ else
SRC_EXT=TOPLANG_NOT_DEFINED
endif
TOPFILE ?= src/Top.$(SRC_EXT)
TOPFILE ?= bs/Top.$(SRC_EXT)
TOPMODULE ?= mkTop
BSC_COMP_FLAGS += \
@ -61,7 +61,7 @@ $(BDPI_OBJ): $(BDPI_SRC)
BSC_LINK_FLAGS += -keep-fires
BSC_PATHS = -p src/:+
BSC_PATHS = -p bs/:bsv/:+
.PHONY: help
help:

3
README.md
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@ -1,7 +1,8 @@
# MannaChip
## Introduction:
Manna was the miraculous food provided by God requiring no effort on behalf of the Israelites. In a similar vein, the MannaChip processor delivers groundbreaking performance, necessitating minimal intervention on the developer's or user's part.
Manna was the miraculous food provided by God requiring no effort on behalf of the Israelites. In a similar vein, the POWER3.0 compliant MannaChip
processor delivers groundbreaking performance, necessitating minimal intervention on the developer's or user's part.
Just as "man does not live by bread alone, but by every word that proceeds from the mouth of God," this chip thrives on every instruction word you provide. It's not just about raw computational power, but the synergy between user input and hardware optimization.

40
bs/ClkDivider.bs Normal file
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@ -0,0 +1,40 @@
package ClkDivider(mkClkDivider, ClkDivider(..)) where
interface (ClkDivider :: # -> *) hi =
{
reset :: Action
;isAdvancing :: Bool
;isHalfCycle :: Bool
}
mkClkDivider :: Handle -> Module (ClkDivider hi)
mkClkDivider fileHandle = do
counter <- mkReg(0 :: UInt (TLog hi))
let hi_value :: UInt (TLog hi) = (fromInteger $ valueOf hi)
let half_hi_value :: UInt (TLog hi) = (fromInteger $ valueOf (TDiv hi 2))
let val :: Real = (fromInteger $ valueOf hi)
let msg = "Clock Div Period : " + (realToString val) + "\n"
hPutStr fileHandle msg
hPutStr fileHandle genModuleName
addRules $
rules
{-# ASSERT fire when enabled #-}
{-# ASSERT no implicit conditions #-}
"tick" : when True ==> action
$display (counter)
counter := if (counter == hi_value)
then 0
else counter + 1
return $
interface ClkDivider
reset :: Action
reset = do
counter := 0
isAdvancing :: Bool
isAdvancing = (counter == hi_value)
isHalfCycle = (counter == half_hi_value)

40
bs/Core.bs Normal file
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@ -0,0 +1,40 @@
package Core(Core(..), mkCore) where
import ClkDivider
import Prelude
interface (Core :: # -> *) clkFreq = {
getChar :: Bit 8
;getLed :: Bit 8
;putChar :: Bit 8 -> Action
}
mkCore :: Module (Core clkFreq)
mkCore = do
counter :: Reg (UInt (TLog clkFreq)) <- mkReg 0
tickSecond :: Wire Bool <- mkDWire False
uartOut :: Wire (Bit 8) <- mkWire;
ledOut :: Reg (Bit 8) <- mkReg 0
let clkFreqInt :: Integer = valueOf clkFreq
let clkFreqUInt :: UInt (TLog clkFreq) = fromInteger clkFreqInt
let val :: Real = fromInteger clkFreqInt
messageM $ "mkCore clkFreq" + realToString val
let pulseEverySecond :: Bool = (counter == clkFreqUInt)
addRules $
rules
"count" : when True ==>
counter := if (counter == clkFreqUInt) then 0 else (counter + 1)
"countingLed" : when pulseEverySecond ==>
ledOut := ledOut + 1
return $
interface Core
getChar = uartOut
getLed = ledOut
putChar byteIn =
do
uartOut := byteIn

53
bs/Deserializer.bs Normal file
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@ -0,0 +1,53 @@
package Deserializer(
mkDeserialize,
IDeserializer(..),
State(..))
where
import ClkDivider
import State
interface (IDeserializer :: # -> # -> *) clkFreq baudRate =
get :: Bit 8
putBitIn :: (Bit 1) -> Action {-# always_enabled, always_ready #-}
mkDeserialize :: Handle -> Module (IDeserializer clkFreq baudRate)
mkDeserialize fileHandle = do
ftdiRxIn :: Wire(Bit 1) <- mkBypassWire
shiftReg :: Reg(Bit 8) <- mkReg(0)
ftdiState <- mkReg(IDLE)
clkDivider :: (ClkDivider (TDiv clkFreq baudRate)) <- mkClkDivider fileHandle
addRules $
rules
{-# ASSERT fire when enabled #-}
"IDLE" : when (ftdiState == IDLE), (ftdiRxIn == 0) ==>
do
clkDivider.reset
ftdiState := ftdiState' ftdiState
{-# ASSERT fire when enabled #-}
"NOT IDLE" : when (ftdiState /= IDLE), (clkDivider.isAdvancing) ==>
do
ftdiState := ftdiState' ftdiState
{-# ASSERT fire when enabled #-}
"SAMPLING" : when
DATA(n) <- ftdiState,
n >= 0,
n <= 7,
let sampleTrigger = clkDivider.isHalfCycle
in sampleTrigger
==>
do
shiftReg := ftdiRxIn ++ shiftReg[7:1]
return $
interface IDeserializer
{get = shiftReg when (ftdiState == STOP), (clkDivider.isAdvancing)
;putBitIn bit =
ftdiRxIn := bit
}

52
bs/Serializer.bs Normal file
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@ -0,0 +1,52 @@
package Serializer(
mkSerialize,
ISerializer(..),
State(..))
where
import ClkDivider
import State
serialize :: State -> Bit 8 -> Bit 1
serialize ftdiState dataReg =
case ftdiState of
START -> 1'b0
(DATA n) -> dataReg[n:n]
_ -> 1'b1
interface (ISerializer :: # -> # -> *) clkFreq baudRate =
putBit8 :: (Bit 8) -> Action {-# always_enabled, always_ready #-}
bitLineOut :: Bit 1 {-# always_ready #-}
mkSerialize :: Handle -> Module (ISerializer clkFreq baudRate)
mkSerialize fileHandle = do
ftdiTxOut :: Wire(Bit 1) <- mkBypassWire
dataReg :: Reg(Bit 8) <- mkReg(0)
ftdiState <- mkReg(IDLE)
clkDivider :: (ClkDivider (TDiv clkFreq baudRate)) <- mkClkDivider fileHandle
addRules $
rules
{-# ASSERT fire when enabled #-}
"ADVANCE UART STATE WHEN NOT IDLE" : when
(ftdiState /= IDLE),
(clkDivider.isAdvancing) ==>
do
ftdiState := ftdiState' ftdiState
{-# ASSERT fire when enabled #-}
"BIT LINE" : when True ==>
do
ftdiTxOut := serialize ftdiState dataReg
return $
interface ISerializer
putBit8 bit8Val =
do
clkDivider.reset
dataReg := bit8Val
ftdiState := ftdiState' ftdiState
when (ftdiState == IDLE)
bitLineOut = ftdiTxOut

20
bs/State.bs Normal file
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@ -0,0 +1,20 @@
package State(
State(..),
ftdiState') where
data State = IDLE
| START
| DATA (UInt (TLog 8))
| PARITY
| STOP
deriving (Bits, Eq, FShow)
ftdiState' :: State -> State
ftdiState' state =
case state of
IDLE -> START
START -> DATA(0)
DATA(7) -> PARITY
DATA(n) -> DATA(n+1)
PARITY -> STOP
STOP -> IDLE

76
bs/Top.bs Normal file
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@ -0,0 +1,76 @@
package Top(mkTop, ITop(..)) where
import Deserializer
import Core
import Serializer
import BRAM
import CBindings
type FCLK = 25000000
type BAUD = 9600
interface ITop = {
ftdi_rxd :: Bit 1 {-# always_ready #-}
;led :: Bit 8 {-# always_ready #-}
;ftdi_txd :: Bit 1 -> Action {-# always_ready , always_enabled #-}
};
mkTop :: Module ITop
mkTop = do
fileHandle :: Handle <- openFile "compile.log" WriteMode
deserializer :: IDeserializer FCLK BAUD <- mkDeserialize fileHandle
serializer :: ISerializer FCLK BAUD <- mkSerialize fileHandle
core :: Core FCLK <- mkCore
persistLed :: Reg (Bit 8) <- mkReg 0
messageM $ "Hallo!!" + (realToString 5)
-- refactor such that the following rules are let-bound to
-- `attachIO` identifier
addRules $
rules
"coreLedO" : when True ==>
persistLed := core.getLed
"coreCharDeviceO" : when True ==>
serializer.putBit8 core.getChar
"coreCharDeviceO" : when True ==>
serializer.putBit8 core.getChar
"coreCharDeviceI" : when True ==>
core.putChar deserializer.get
return $
interface ITop
ftdi_rxd = serializer.bitLineOut
ftdi_txd bitIn =
do
deserializer.putBitIn bitIn
led = persistLed
mkSim :: Module Empty
mkSim = do
let cfg :: BRAM_Configure = defaultValue
count :: Reg (UInt 3) <- mkReg 0;
initCFunctions :: Reg Bool <- mkReg False;
core :: Core FCLK <- mkCore;
addRules $
rules
"initCFunctionsOnce": when not initCFunctions ==>
do
initTerminal
setupSigintHandler
initCFunctions := True
"coreCharDeviceO": when True ==>
do
writeCharToTerminal core.getChar
"coreCharDeviceI": when (isCharAvailable == 1) ==>
do
core.putChar getCharFromTerminal
"endSim": when wasCtrlCReceived ==>
do
restoreTerminal
$display "GOT CTRL+C"
$finish

50
bsv/CBindings.bsv Normal file
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@ -0,0 +1,50 @@
package CBindings;
// Original function imports
import "BDPI" function Action init_terminal();
import "BDPI" function Action restore_terminal();
import "BDPI" function Bit#(8) get_char_from_terminal();
import "BDPI" function Int#(32) is_char_available();
import "BDPI" function Action write_char_to_terminal(Bit#(8) chr);
import "BDPI" function Action setup_sigint_handler();
import "BDPI" function Bool was_ctrl_c_received();
// Aliased exports
export initTerminal;
export restoreTerminal;
export getCharFromTerminal;
export isCharAvailable;
export writeCharToTerminal;
export setupSigintHandler;
export wasCtrlCReceived;
// Aliased function definitions
function Action initTerminal();
return init_terminal();
endfunction
function Action restoreTerminal();
return restore_terminal();
endfunction
function Bit#(8) getCharFromTerminal();
return get_char_from_terminal();
endfunction
function Int#(32) isCharAvailable();
return is_char_available();
endfunction
function Action writeCharToTerminal(Bit#(8) chr);
return write_char_to_terminal(chr);
endfunction
function Action setupSigintHandler();
return setup_sigint_handler();
endfunction
function Bool wasCtrlCReceived();
return was_ctrl_c_received();
endfunction
endpackage

2
experiments/bram/README.md
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@ -18,6 +18,6 @@ bsc -sim -u -g mkTestbench Testbench.bs; bsc -sim -e mkTestbench -o simBRAM;
## With TCL
```bash
bsc -sim -u -g mkTestbench Testbench.bsv; bsc -sim -e mkTestbench -o simBRAM;
bsc -sim -u -g mkTestbench Testbench.bs; bsc -sim -e mkTestbench -o simBRAM;
bluetcl sim_inspect.tcl
```

42
src/ClkDivider.bsv
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@ -1,42 +0,0 @@
package ClkDivider;
export mkClkDivider;
export ClkDivider(..);
interface ClkDivider#(numeric type hi);
method Action reset();
method Bool isAdvancing();
method Bool isHalfCycle();
endinterface
module mkClkDivider#(Handle fileHandle)(ClkDivider#(hi));
Reg#(UInt#(TLog#(hi))) counter <- mkReg(0);
UInt#(TLog#(hi)) hi_value = fromInteger(valueOf(hi));
UInt#(TLog#(hi)) half_hi_value = fromInteger(valueOf(TDiv#(hi, 2)));
Real val = fromInteger(valueOf(hi));
let msg = "Clock Div Period : " + realToString(val) + "\n";
hPutStr(fileHandle, msg);
hPutStr(fileHandle, genModuleName);
(* fire_when_enabled, no_implicit_conditions *)
rule tick;
// $display(counter);
counter <= (counter == hi_value) ? 0 : counter + 1;
endrule
method Action reset();
counter <= 0;
endmethod
method Bool isAdvancing();
return (counter == hi_value);
endmethod
method Bool isHalfCycle();
return (counter == half_hi_value);
endmethod
endmodule
endpackage

47
src/Core.bsv
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@ -1,47 +0,0 @@
package Core;
import ClkDivider::*;
import Prelude::*;
interface Core#(numeric type clkFreq);
method Bit#(8) get_char();
method Bit#(8) get_led();
method Action put_char(Bit#(8) byte_in);
endinterface
module mkCore(Core#(clkFreq));
// Reg # (UInt # (32)) counter <- mkReg(0);
Reg # (UInt # (TLog # (clkFreq))) counter <- mkReg(0);
Wire # (Bool) tick_second <- mkDWire(False);
Wire # (Bit # (8)) uart_out <- mkWire;
Reg # (Bit # (8)) led_out <- mkReg(0);
Integer clkFreqInt = valueOf(clkFreq);
UInt#(TLog#(clkFreq)) clkFreqUInt = fromInteger(clkFreqInt);
Real val = fromInteger(clkFreqInt);
messageM("mkCore clkFreq" + realToString(val));
Bool pulse_every_second = counter == clkFreqUInt;
rule count;
counter <= (counter == clkFreqUInt) ? 0 : counter + 1;
endrule
rule counting_led(pulse_every_second);
led_out <= led_out + 1;
endrule
method Bit#(8) get_char();
return uart_out;
endmethod
method Bit#(8) get_led();
return led_out;
endmethod
method Action put_char(Bit#(8) byte_in);
Bit#(8) value = byte_in;
uart_out <= value;
// led_out <= value;
endmethod
endmodule
endpackage

55
src/Deserializer.bsv
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@ -1,55 +0,0 @@
package Deserializer;
export mkDeserialize;
export IDeserializer(..);
export State(..);
import ClkDivider::*;
import State::*;
interface IDeserializer#(numeric type clkFreq, numeric type baudRate);
method Bit#(8) get();
(* always_enabled , always_ready *)
method Action putBitIn(Bit#(1) bitIn);
endinterface
module mkDeserialize#(Handle fileHandle)(IDeserializer#(clkFreq, baudRate));
Wire#(Bit#(1)) ftdiRxIn <- mkBypassWire;
Reg#(Bit#(8)) shiftReg <- mkReg(0);
Reg#(State) ftdiState <- mkReg(IDLE);
ClkDivider#(TDiv#(clkFreq, baudRate)) clkDivider <- mkClkDivider(fileHandle);
(* fire_when_enabled *)
rule idle (ftdiState == IDLE && ftdiRxIn == 0);
clkDivider.reset();
ftdiState <= ftdiStateNext(ftdiState);
endrule
(* fire_when_enabled *)
rule not_idle (ftdiState != IDLE && clkDivider.isAdvancing());
ftdiState <= ftdiStateNext(ftdiState);
endrule
(* fire_when_enabled *)
rule sampling (
ftdiState matches (tagged DATA .n) &&&
clkDivider.isHalfCycle()
);
shiftReg <= {ftdiRxIn, shiftReg[7:1]};
endrule
// an invariant enforced here is we can't call this method
// until shift reg is valid
method Bit#(8) get() if (ftdiState == STOP && clkDivider.isAdvancing());
return shiftReg;
endmethod
method Action putBitIn(Bit#(1) bitIn);
ftdiRxIn <= bitIn;
endmethod
endmodule
endpackage

53
src/Serializer.bsv
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@ -1,53 +0,0 @@
package Serializer;
import ClkDivider::*;
import State::*;
export mkSerialize;
export ISerializer(..);
export State(..);
function Bit#(1) serialize(State state, Bit#(8) dataReg);
case (state) matches
tagged START : return 1'b0;
tagged DATA .n : return dataReg[n];
default : return 1'b1;
endcase
endfunction
interface ISerializer#(numeric type clkFreq, numeric type baudRate);
(* always_enabled , always_ready *)
method Action putBit8(Bit#(8) bit8Val);
(* always_ready *)
method Bit#(1) bitLineOut();
endinterface
module mkSerialize#(Handle fileHandle)(ISerializer#(clkFreq, baudRate));
Wire#(Bit#(1)) ftdiTxOut <- mkDWire(1);
Reg#(Bit#(8)) dataReg <- mkReg(0);
Reg#(State) ftdiState <- mkReg(IDLE);
ClkDivider#(TDiv#(clkFreq, baudRate)) clkDivider <- mkClkDivider(fileHandle);
(* fire_when_enabled *)
rule advanceUartState (ftdiState != IDLE && clkDivider.isAdvancing());
ftdiState <= ftdiStateNext(ftdiState);
endrule
(* fire_when_enabled *)
rule bitLine (ftdiState != IDLE);
ftdiTxOut <= serialize(ftdiState, dataReg);
endrule
method Action putBit8(Bit#(8) bit8Val) if (ftdiState == IDLE);
clkDivider.reset();
dataReg <= bit8Val;
ftdiState <= ftdiStateNext(ftdiState);
endmethod
method Bit#(1) bitLineOut;
return ftdiTxOut;
endmethod
endmodule
endpackage

32
src/State.bsv
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@ -1,32 +0,0 @@
package State;
export State(..);
export ftdiStateNext;
typedef union tagged {
void IDLE;
void START;
UInt#(TLog#(8)) DATA;
void PARITY;
void STOP;
} State deriving (Bits, Eq, FShow);
function State ftdiStateNext(State state);
return
case (state) matches
tagged IDLE : START;
tagged START : DATA(0);
tagged DATA .n :
begin
if (n == 7)
PARITY;
else
DATA(n + 1);
end
tagged PARITY : STOP;
tagged STOP : IDLE;
endcase
;
endfunction
endpackage

104
src/Top.bsv
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@ -1,104 +0,0 @@
package Top;
export mkTop;
export ITop(..);
// export mkSim;
import "BDPI" function Action init_terminal();
import "BDPI" function Action restore_terminal();
import "BDPI" function Bit#(8) get_char_from_terminal();
import "BDPI" function Int#(32) is_char_available();
import "BDPI" function Action write_char_to_terminal(Bit#(8) chr);
import "BDPI" function Action setup_sigint_handler();
import "BDPI" function Bool was_ctrl_c_received();
import Deserializer::*;
import Core::*;
import Serializer::*;
import BRAM::*;
typedef 25000000 FCLK;
typedef 9600 BAUD;
interface ITop;
(* always_ready *)
method Bit # (1) ftdi_rxd();
(* always_ready *)
method Bit # (8) led();
(* always_enabled , always_ready *)
method Action ftdi_txd(Bit#(1) bitIn);
endinterface
(* synthesize *)
module mkTop(ITop);
Handle fileHandle <- openFile("compile.log", WriteMode);
IDeserializer # (FCLK, BAUD) deserializer <- mkDeserialize(fileHandle);
ISerializer # (FCLK, BAUD) serializer <- mkSerialize(fileHandle);
Core # (FCLK) core <- mkCore();
Reg#(Bit#(8)) persist_led <- mkReg(0);
messageM("Hallo!!" + realToString(5));
// connect up core device
rule core_led_o;
persist_led <= core.get_led;
endrule
rule core_char_device_o;
serializer.putBit8(core.get_char);
endrule
rule core_char_device_i;
core.put_char(deserializer.get);
endrule
// output methods
method Bit#(1) ftdi_rxd;
return serializer.bitLineOut;
endmethod
method Action ftdi_txd(Bit#(1) bitIn);
deserializer.putBitIn(bitIn);
endmethod
method Bit#(8) led;
return persist_led;
endmethod
endmodule
module mkSim(Empty);
BRAM_Configure cfg = defaultValue;
// Define a 3-bit register named count
Reg#(UInt#(3)) count <- mkReg(0);
Reg#(Bool) init_C_functions <- mkReg(False);
Core#(FCLK) core <- mkCore();
rule init_c_functions_once (!init_C_functions);
init_terminal();
setup_sigint_handler();
init_C_functions <= True;
endrule
// implicit true - should always fire - effective making
// a loopback
rule core_char_device_o;
write_char_to_terminal(core.get_char);
endrule
rule core_char_device_i(is_char_available() == 1);
core.put_char(get_char_from_terminal());
endrule
// Rule to finish the simulation when count reaches 6
rule end_sim (was_ctrl_c_received());
restore_terminal();
$display("GOT CTRL+C");
($finish)();
endrule
endmodule
endpackage