26 lines
348 B
Plaintext
26 lines
348 B
Plaintext
*.vcd
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*.so
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# bluespec files
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*.bo
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*.ba
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# files generated from building/simulating core
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compile.log
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build_v
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build_b_sim
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mkSim_b_sim
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verilog_RTL
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# files generated for FPGA ULX3s implementation
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ulx3s_fpga/mkTop.d
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ulx3s_fpga/mkTop.json
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# generated experiment outputs
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experiments/bram/*.cxx
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experiments/bram/*.h
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experiments/bram/simBRAM
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*.o
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.vscode
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