clean unused experiments
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e89254ebef
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bs/Top.bs
44
bs/Top.bs
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@ -21,44 +21,6 @@ interface ITop = {
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;ftdi_txd :: Bit 1 -> Action {-# always_ready , always_enabled #-}
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;ftdi_txd :: Bit 1 -> Action {-# always_ready , always_enabled #-}
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};
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};
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interface BusClient =
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request :: Bit 1
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response :: Bit 1 -> Action
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mkBusClient :: Module BusClient
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mkBusClient = module
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reqReg :: Reg (Bit 1) <- mkReg 0
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return $
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interface BusClient
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request = reqReg
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response resp = do
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reqReg := 0 -- Reset request after receiving response
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interface Bus =
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request :: Bit 1 -> Action
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response :: Bit 1
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mkBus :: Module Bus
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mkBus = module
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respReg :: Reg (Bit 1) <- mkReg 0
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return $
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interface Bus
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request req = do
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respReg := req -- Simple pass-through for this example
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response = respReg
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-- -- Function to connect Bus to BusClient
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connectBusToClient :: Bus -> BusClient -> Rules
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connectBusToClient bus client =
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rules
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"busConnection": when True ==> do
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bus.request client.request
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client.response bus.response
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-- need to implement mkBus
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-- need function that can connect Bus to BusClient
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mkTop :: Module ITop
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mkTop :: Module ITop
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mkTop = do
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mkTop = do
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fileHandle :: Handle <- openFile "compile.log" WriteMode
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fileHandle :: Handle <- openFile "compile.log" WriteMode
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@ -66,15 +28,9 @@ mkTop = do
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serializer :: ISerializer FCLK BAUD <- mkSerialize fileHandle
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serializer :: ISerializer FCLK BAUD <- mkSerialize fileHandle
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core :: Core FCLK <- mkCore
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core :: Core FCLK <- mkCore
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bus :: Bus <- mkBus
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busClient :: BusClient <- mkBusClient
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persistLed :: Reg (Bit 8) <- mkReg 0
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persistLed :: Reg (Bit 8) <- mkReg 0
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messageM $ "Hallo!!" + (realToString 5)
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messageM $ "Hallo!!" + (realToString 5)
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-- need to instantiate a Bus and BusClient
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addRules $ connectBusToClient bus busClient
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addRules $
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addRules $
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rules
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rules
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-- need new rule that always connects Bus to BusClient
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-- need new rule that always connects Bus to BusClient
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