still workikng on Bus types
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@ -1,4 +1,10 @@
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package BusTypes(BusVal, TransactionSize) where
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package BusTypes(
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BusVal(..),
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BusError(..),
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TransactionSize(..),
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ReadRequest(..),
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WriteRequest(..)
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) where
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import Types
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import Types
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@ -29,5 +35,34 @@ data ReadRequest = ReadRequest Addr TransactionSize
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data WriteRequest = WriteRequest Addr BusVal
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data WriteRequest = WriteRequest Addr BusVal
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deriving (Bits, Eq, FShow)
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deriving (Bits, Eq, FShow)
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type ReadResponse = Either BusError BusVal
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type WriteResponse = Either BusError ()
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data BusRequest
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= BusReadRequest ReadRequest
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| WriteReadRequest WriteRequest
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deriving (Bits, Eq, FShow)
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data BusResponse
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= BusReadResponse ReadResponse
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| BusWriteResponse WriteResponse
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deriving (Bits, Eq, FShow)
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interface BusMaster =
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-- The Bus arbiter will call the Bus Client's request method
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-- if and only if it's the Bus Client's turn to make a request, and the Bus Client
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-- has a request to make.
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-- It is up to the BusMaster to guard it's request method such that calling
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-- it's request method is only valid when the BusMaster has a request to make.
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-- This has implications about for the implementor of BusMaster, namely, that it
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-- should hold its request until it's request method gets called.
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request :: BusRequest
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-- From the client's perspective, the response should not be called until
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-- the client is ready to accept the response. In other words, response
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-- should be guarded by the client.
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response :: BusResponse -> Action
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type Token = UInt 5
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a :: UInt 5
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a :: UInt 5
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a = 3
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a = 3
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51
bs/Top.bs
51
bs/Top.bs
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@ -6,6 +6,7 @@ import Serializer
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import BRAM
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import BRAM
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import CBindings
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import CBindings
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import Bus
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import Bus
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import List
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type FCLK = 25000000
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type FCLK = 25000000
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type BAUD = 9600
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type BAUD = 9600
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@ -16,19 +17,65 @@ interface ITop = {
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;ftdi_txd :: Bit 1 -> Action {-# always_ready , always_enabled #-}
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;ftdi_txd :: Bit 1 -> Action {-# always_ready , always_enabled #-}
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};
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};
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interface BusClient =
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request :: Bit 1
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response :: Bit 1 -> Action
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mkBusClient :: Module BusClient
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mkBusClient = module
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reqReg :: Reg (Bit 1) <- mkReg 0
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return $
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interface BusClient
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request = reqReg
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response resp = do
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reqReg := 0 -- Reset request after receiving response
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interface Bus =
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request :: Bit 1 -> Action
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response :: Bit 1
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mkBus :: Module Bus
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mkBus = module
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respReg :: Reg (Bit 1) <- mkReg 0
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return $
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interface Bus
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request req = do
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respReg := req -- Simple pass-through for this example
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response = respReg
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-- -- Function to connect Bus to BusClient
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connectBusToClient :: Bus -> BusClient -> Rules
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connectBusToClient bus client =
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rules
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"busConnection": when True ==> do
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bus.request client.request
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client.response bus.response
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-- need to implement mkBus
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-- need function that can connect Bus to BusClient
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mkTop :: Module ITop
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mkTop :: Module ITop
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mkTop = do
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mkTop = do
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fileHandle :: Handle <- openFile "compile.log" WriteMode
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fileHandle :: Handle <- openFile "compile.log" WriteMode
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deserializer :: IDeserializer FCLK BAUD <- mkDeserialize fileHandle
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deserializer :: IDeserializer FCLK BAUD <- mkDeserialize fileHandle
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serializer :: ISerializer FCLK BAUD <- mkSerialize fileHandle
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serializer :: ISerializer FCLK BAUD <- mkSerialize fileHandle
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core :: Core FCLK <- mkCore
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core :: Core FCLK <- mkCore
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bus :: Bus <- mkBus
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busClient :: BusClient <- mkBusClient
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let a :: List Integer = 1 :> 2 :> Nil
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b = length a
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persistLed :: Reg (Bit 8) <- mkReg 0
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persistLed :: Reg (Bit 8) <- mkReg 0
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messageM $ "Hallo!!" + (realToString 5)
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messageM $ "Hallo!!" + (realToString 5)
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-- refactor such that the following rules are let-bound to
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-- need to instantiate a Bus and BusClient
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-- `attachIO` identifier
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addRules $ connectBusToClient bus busClient
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addRules $
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addRules $
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rules
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rules
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-- need new rule that always connects Bus to BusClient
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"coreLedO" : when True ==>
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"coreLedO" : when True ==>
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persistLed := core.getLed
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persistLed := core.getLed
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