Artturin/riscv-bluespec-classic
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improve some indentation in src/Top.bsv

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Yehowshua Immanuel 2024-03-20 02:49:08 -04:00
parent 95631e77b8
commit 423ea6142e
2 changed files with 5 additions and 2 deletions
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2
.gitignore vendored
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@ -8,6 +8,8 @@
# files generated from building/simulating core # files generated from building/simulating core
compile.log compile.log
build_v build_v
build_b_sim
mkSim_b_sim
verilog_RTL verilog_RTL
# generated experiment outputs # generated experiment outputs

5
src/Top.bsv
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@ -81,10 +81,11 @@ module mkSim(Empty);
endrule endrule
rule core_char_device_o; rule core_char_device_o;
write_char_to_terminal(core.get_char); write_char_to_terminal(core.get_char);
endrule endrule
rule core_char_device_i(is_char_available() == 1); rule core_char_device_i(is_char_available() == 1);
core.put_char(get_char_from_terminal()); core.put_char(get_char_from_terminal());
endrule endrule
// Rule to finish the simulation when count reaches 6 // Rule to finish the simulation when count reaches 6