diff --git a/.gitignore b/.gitignore
index 8c3232b..4225498 100644
--- a/.gitignore
+++ b/.gitignore
@@ -8,6 +8,8 @@
 # files generated from building/simulating core
 compile.log
 build_v
+build_b_sim
+mkSim_b_sim
 verilog_RTL
 
 # generated experiment outputs
diff --git a/src/Top.bsv b/src/Top.bsv
index 0a95dbe..563f02d 100644
--- a/src/Top.bsv
+++ b/src/Top.bsv
@@ -81,10 +81,11 @@ module mkSim(Empty);
 	endrule
 
     rule core_char_device_o;
-		write_char_to_terminal(core.get_char);
+      write_char_to_terminal(core.get_char);
     endrule
+
     rule core_char_device_i(is_char_available() == 1);
-		core.put_char(get_char_from_terminal());
+      core.put_char(get_char_from_terminal());
     endrule
 
     // Rule to finish the simulation when count reaches 6