forked from Yehowshua/RiscV-Formal
84 lines
2.2 KiB
Haskell
84 lines
2.2 KiB
Haskell
{-# LANGUAGE GADTs #-}
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{-# LANGUAGE DataKinds #-}
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{-# LANGUAGE TypeOperators #-}
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{-# LANGUAGE ConstraintKinds #-}
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module Simulation(
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Args(..),
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simulation,
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RISCVCPU(..),
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Machine(..),
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Simulation(..)
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) where
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import qualified Prelude as P
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import Peripherals.Setup(setupPeripherals, InitializedPeripherals(..))
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import Peripherals.Teardown(teardownPeripherals)
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import Clash.Prelude
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import Bus(Peripherals(..))
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import Cpu(
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RISCVCPU(..),
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riscvCPUInit)
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import Fetch(fetchInstruction, FetchResult (..))
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import Isa.Decode(decode)
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import Debug.Trace
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import Types (Insn)
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import Control.Monad.RWS (MonadState(put))
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data Args = Args {
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firmware :: FilePath
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} deriving (Show)
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data Simulation
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= Success [Machine]
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| Failure String
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deriving (Show)
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data Machine = Machine
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{ cpu :: RISCVCPU,
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peripherals :: Peripherals
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}
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deriving (Generic, Show, Eq, NFDataX)
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debugInsn :: FetchResult -> String
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debugInsn fetchResult =
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case fetchResult of
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Instruction insn ->
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"Decoded instruction: " P.++ show opcode
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P.++ " | Binary: " P.++ binaryInsn
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P.++ " (" P.++ show insn P.++ ")"
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where
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binaryInsn = show (bitCoerce insn :: BitVector 32)
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opcode = decode insn
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InstructionException e -> show e
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simulationLoop :: Int -> Machine -> IO [Machine]
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simulationLoop 0 machine = return [machine]
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simulationLoop n machine = do
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let machinePeripherals = peripherals machine
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currPc = pc $ cpu machine
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fetchResult <- fetchInstruction machinePeripherals currPc
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putStrLn $ debugInsn fetchResult
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let pc' = currPc + 4
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cpu' = (cpu machine) { pc = pc' }
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machine' = machine { cpu = cpu' }
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rest <- simulationLoop (n - 1) machine'
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return (machine : rest)
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simulation :: Args -> IO Simulation
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simulation args = do
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initializedPeripherals <- setupPeripherals (firmware args)
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case initializedPeripherals of
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InitializationError e -> return $ Failure e
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InitializedPeripherals ram -> do
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let initState =
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Machine {
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cpu = riscvCPUInit,
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peripherals = Bus.Peripherals ram
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}
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sim <- simulationLoop 15 initState
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teardownPeripherals
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return $ Success sim
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