Yehowshua
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Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-05 04:37:43 +00:00
eb79210863 now using bus and new FetchResult type
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-05 04:05:55 +00:00
4729d79b23 refactoring towards types that can handle exceptions between stages
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-04 13:13:04 +00:00
d7d698a28c save progress before switching to new bus architecture
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-03-03 04:12:06 +00:00
88ec010f98 initial support for exceptions
Yehowshua opened issue Yehowshua/RiscV-Formal#9 2025-03-02 08:02:30 +00:00
Add Mtime peripheral
Yehowshua opened issue Yehowshua/RiscV-Formal#8 2025-03-02 07:16:41 +00:00
Implement Exception Handling in Exceptions.hs
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-02-26 18:05:06 +00:00
5552ad3d4a bus architecture re-built I think
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-02-26 07:24:27 +00:00
c8b192cade prep for notable re-org
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-02-26 06:51:37 +00:00
024115e389 Uart now has correct write implementation presumably
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-02-26 04:47:04 +00:00
8d5cd862ab more progress on UART read
Yehowshua opened issue Yehowshua/RiscV-Formal#7 2025-02-26 00:57:04 +00:00
Processor Errata
Yehowshua opened issue Yehowshua/RiscV-Formal#6 2025-02-26 00:14:39 +00:00
Go through and clean up warnings
Yehowshua commented on issue Yehowshua/RiscV-Formal#2 2025-02-26 00:14:13 +00:00
Generalize Memory Access

getting there...

Yehowshua commented on issue Yehowshua/RiscV-Formal#3 2025-02-26 00:13:52 +00:00
Handle Compressed Instructions

Will not support.

Yehowshua closed issue Yehowshua/RiscV-Formal#3 2025-02-26 00:13:52 +00:00
Handle Compressed Instructions
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-02-26 00:09:41 +00:00
7265728932 read getting closer to being done
Yehowshua pushed to main at Yehowshua/RiscV-Formal 2025-02-25 19:24:59 +00:00
1f9bd2f015 hopefully progressing to a more scalable bus architecture
Yehowshua opened issue Yehowshua/RiscV-Formal#5 2025-02-25 16:50:04 +00:00
Indicate that the Formal Model will not Support C(compressed instructions)
Yehowshua commented on issue Yehowshua/RiscV-Formal#3 2025-02-20 01:29:06 +00:00
Handle Compressed Instructions

I think the fetch unit itself should be responsible for assembling 32 bit instructions.

Yehowshua opened issue Yehowshua/RiscV-Formal#3 2025-02-20 01:24:50 +00:00
Handle Compressed Instructions