54 lines
1.5 KiB
Haskell
54 lines
1.5 KiB
Haskell
{-# LANGUAGE DataKinds #-}
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{-# LANGUAGE NumericUnderscores #-}
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module Fetch(
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fetchInstruction,
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FetchResult(..)) where
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import Clash.Prelude
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import Types(Mem, Addr, Insn)
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import Bus(ReadResponse, WriteResponse, read)
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import Bus(Peripherals(..))
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import BusTypes(
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ReadRequest(..),
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TransactionSize(..),
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BusVal(..),
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BusError(..))
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import Exceptions(Exception(..), exceptionCode, isSynchronousException)
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import GHC.IO (IO)
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import GHC.Base (Applicative(pure))
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data FetchResult = Instruction Insn
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| Misaligned Addr
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data FetchResult1 = Instruction1 Insn
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| InstructionException Exception
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fetchInstruction :: KnownNat n => Mem n -> Addr -> FetchResult
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fetchInstruction mem addr =
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let
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isWordAligned = addr .&. 3 == 0
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addrWordAligned = addr `shiftR` 2
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insn = mem !! addrWordAligned
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-- TODO : check if instruction is word aligned and create type
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-- to capture if its not.
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in
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case isWordAligned of
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True -> Instruction insn
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False -> Misaligned addr
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fetchInstruction1 :: Peripherals -> Addr -> IO FetchResult1
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fetchInstruction1 peripherals addr =
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do
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readReasponse <-Bus.read (BusTypes.Request addr BusTypes.SizeFullWord) peripherals
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case readReasponse of
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Right (BusFullWord insn) ->
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pure $ Instruction1 insn
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Left UnAligned ->
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pure $ InstructionException InstructionAddressMisaligned
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Left UnMapped ->
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pure $ InstructionException InstructionAccessFault
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Right _ ->
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pure $ InstructionException InstructionAccessFault
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