RiscV-Formal/hs/Fetch.hs
2025-03-04 23:54:30 -05:00

36 lines
959 B
Haskell

{-# LANGUAGE DataKinds #-}
{-# LANGUAGE NumericUnderscores #-}
module Fetch(
fetchInstruction,
FetchResult(..),
) where
import Clash.Prelude
import Types(Addr, Insn)
import Bus(read)
import Bus(Peripherals(..))
import BusTypes(
ReadRequest(..),
TransactionSize(..),
BusVal(..),
BusError(..))
import Exceptions(Exception(..))
data FetchResult = Instruction Insn
| InstructionException Exception
fetchInstruction :: Peripherals -> Addr -> IO FetchResult
fetchInstruction peripherals addr =
do
readReasponse <-Bus.read (BusTypes.Request addr BusTypes.SizeFullWord) peripherals
case readReasponse of
Right (BusFullWord insn) ->
pure $ Instruction insn
Left UnAligned ->
pure $ InstructionException InstructionAddressMisaligned
Left UnMapped ->
pure $ InstructionException InstructionAccessFault
Right _ ->
pure $ InstructionException InstructionAccessFault