99 lines
4.4 KiB
Haskell
99 lines
4.4 KiB
Haskell
{-# LANGUAGE DataKinds #-}
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{-# LANGUAGE NumericUnderscores #-}
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-- | This module defines the register files used in a RISC-V core, including:
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-- General Purpose Registers (GPR), Floating Point Registers (FPR), and Control & Status Registers (CSR).
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--
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-- In RISC-V, besides the GPR, FPR, and CSR, we may also encounter
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-- the following which are not modeled in this codebase:
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-- * VRF (Vector Registers File) for vector processing.
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-- * Debug Registers (DBR) for hardware debugging.
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-- * Shadow Registers for fast context switching (optional).
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-- * MPU Registers for memory protection.
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-- * Counter/Timer Registers for time/cycle counting.
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-- * Hypervisor Registers (HPR) for guest virtualization.
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module RegFiles(
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RegFileIdx,
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RegVal(..),
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GPR,
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FPR,
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CSR,
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gprInit,
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fprInit,
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csrInit
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) where
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import Clash.Prelude
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import Util((|>))
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import Types(DoubleWord)
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type RegFileIdx = Unsigned 5
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data RegVal = Value {
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regFileIdx :: RegFileIdx,
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regVal :: DoubleWord
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}
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| Unpopulated {regFileIdx :: RegFileIdx}
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deriving (Generic, Show, Eq, NFDataX)
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type GPR = Vec 32 (Unsigned 64) -- General Purpose Registers
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type FPR = Vec 32 (Unsigned 64) -- Floating Point Registers
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type CSR = Vec 4096 (Unsigned 64) -- Control and Status Registers
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gprInit :: GPR
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gprInit = repeat 0
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fprInit :: FPR
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fprInit = repeat 0
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-- | The 'CSRName' data type enumerates a subset of RISC-V CSRs (Control and Status Registers)
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-- that are modeled in this codebase. Each variant represents a particular CSR.
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data CSRName =
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STVEC -- ^ Supervisor Trap-Vector Base Address: Base address for supervisor mode exception handlers.
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| SEPC -- ^ Supervisor Exception Program Counter: Holds the return address for supervisor mode exceptions.
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| MSTATUS -- ^ Machine Status Register: Contains global machine status flags and control bits.
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| MISA -- ^ Machine ISA Register: Indicates the supported ISA extensions and width.
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| MTVEC -- ^ Machine Trap-Vector Base Address: Base address for machine mode exception handlers.
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| MEPC -- ^ Machine Exception Program Counter: Holds the return address for machine mode exceptions.
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| MVENDORID -- ^ Machine Vendor ID: Identifies the vendor of the processor.
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| MARCHID -- ^ Machine Architecture ID: Identifies the architecture of the processor.
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| MIMPID -- ^ Machine Implementation ID: Identifies the implementation of the processor.
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deriving (Generic, Show, Eq, NFDataX)
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-- | Map each 'CSRName' variant to its corresponding CSR address.
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csrNameToAddr :: CSRName -> Integer
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csrNameToAddr STVEC = 0x105 -- Address for Supervisor Trap-Vector
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csrNameToAddr SEPC = 0x141 -- Address for Supervisor Exception PC
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csrNameToAddr MSTATUS = 0x300
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csrNameToAddr MISA = 0x301
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csrNameToAddr MTVEC = 0x305
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csrNameToAddr MEPC = 0x341 -- Address for Machine Exception PC
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csrNameToAddr MVENDORID = 0xF11
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csrNameToAddr MARCHID = 0xF12
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csrNameToAddr MIMPID = 0xF13
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-- | Initial CSR values.
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-- Note: The CSR registers are not all zero during proper initialization; these values
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-- are placeholders to be revisited for proper initialization later.
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csrInit :: CSR
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csrInit =
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replace (csrNameToAddr STVEC) stvec_init |>
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replace (csrNameToAddr SEPC) sepc_init |>
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replace (csrNameToAddr MSTATUS) mstatus_init |>
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replace (csrNameToAddr MISA) misa_init |>
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replace (csrNameToAddr MTVEC) mtvec_init |>
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replace (csrNameToAddr MEPC) mepc_init |>
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replace (csrNameToAddr MVENDORID) mvendorid_init |>
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replace (csrNameToAddr MARCHID) marchid_init |>
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replace (csrNameToAddr MIMPID) mimpid_init |>
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repeat 0
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where
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stvec_init = 0x0000000000002000 -- Supervisor mode trap vector base address.
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sepc_init = 0x0000000000000000 -- Supervisor Exception PC initial value.
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mstatus_init = 0x0000000000001800 -- Default machine status.
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misa_init = 0x8000000000001104 -- RV64IMAFD: Machine ISA with standard extensions.
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mtvec_init = 0x0000000000001000 -- Machine mode trap vector base address.
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mepc_init = 0x0000000000000000 -- Machine Exception PC initial value.
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mvendorid_init = 0x00000000 -- Vendor-specific ID.
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marchid_init = 0x00000000 -- Architecture-specific ID.
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mimpid_init = 0x00000000 -- Implementation-specific ID.
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