57 lines
1.7 KiB
Haskell
57 lines
1.7 KiB
Haskell
{-# LANGUAGE DataKinds #-}
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{-# LANGUAGE NumericUnderscores #-}
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module RegFiles(
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GPR,
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FPR,
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CSR,
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gprInit,
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fprInit,
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csrInit
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) where
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import Clash.Prelude
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-- In RISC-V, besides the GPR, FPR, and CSR, we may also encounter
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-- the following which are not modeled in this codebase.
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-- * VRF(Vector Registers File) for vector processing.
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-- * Debug Registers (DBR) for hardware debugging.
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-- * Shadow Registers for fast context switching (optional).
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-- * MPU Registers for memory protection.
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-- * Counter/Timer Registers for time/cycle counting.
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-- * Hypervisor Registers (HPR) for guest virtualization.
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type GPR = Vec 32 (Unsigned 64)
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type FPR = Vec 32 (Unsigned 64)
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type CSR = Vec 4096 (Unsigned 64)
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gprInit :: GPR
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gprInit = repeat 0
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fprInit :: FPR
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fprInit = repeat 0
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-- TODO: CSR can't actually be all 0 during initialization.
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-- We need to revisit the following and properly initialize
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-- various registers later.
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csrInit :: CSR
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csrInit =
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replace (0x301 :: Integer) misa_init
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$ replace (0x300 :: Integer) mstatus_init
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$ replace (0x305 :: Integer) mtvec_init
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$ replace (0xF11 :: Integer) mvendorid_init
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$ replace (0xF12 :: Integer) marchid_init
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$ replace (0xF13 :: Integer) mimpid_init
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$ replace (0x701 :: Integer) mtime_init
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$ replace (0x321 :: Integer) mtimecmp_init
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$ repeat 0
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where
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misa_init = 0x8000000000001104 -- `RV64IMAFD`
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mstatus_init = 0x0000000000001800 -- Default `mstatus`
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mtvec_init = 0x0000000000001000 -- Trap vector base
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mvendorid_init = 0x00000000
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marchid_init = 0x00000000
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mimpid_init = 0x00000000
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mtime_init = 0x0000000000000000
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mtimecmp_init = 0xFFFFFFFFFFFFFFFF
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