{-# LANGUAGE DataKinds #-}
{-# LANGUAGE NumericUnderscores #-}

module Cpu(
  RISCVCPU(..),
  Endian(..),
  riscvCPUInit) where

import Clash.Prelude
import Types(Pc)
import RegFiles(GPR, FPR, CSR, gprInit, fprInit, csrInit)

data Endian = Big | Little
  deriving (Generic, Show, Eq, NFDataX)

data PrivilegeLevel
  = MachineMode
  | SuperVisorMode
  | UserMode
  deriving (Generic, Show, Eq, NFDataX)

data RISCVCPU = RISCVCPU
  { pc  :: Pc,
    gpr :: GPR,
    fpr :: FPR,
    csr :: CSR,
    privilegeLevel :: PrivilegeLevel
  }
  deriving (Generic, Show, Eq, NFDataX)

riscvCPUInit :: RISCVCPU
riscvCPUInit =
  RISCVCPU
    { pc = 0x8000_0000
    , gpr = gprInit
    , fpr = fprInit
    , csr = csrInit
    , privilegeLevel = MachineMode
    }