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Processor Errata #7

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opened 2025-02-26 00:57:04 +00:00 by Yehowshua · 0 comments
Yehowshua commented 2025-02-26 00:57:04 +00:00
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Errata that is specific to implementation choices made during the design of this processor.

  • A LoadDoubleWord transaction to our 16550 Uart reg is UB, so we'll make it return what LoadByte would return. Really - any transaction against a Uart reg address larger than Byte e.g. LoadHalfWord or StoreHalfWord should return the same as the Byte transaction, but zero-padded.
  • any cache implementations must be aware of non-cacheable IO in machine mode
  • The Linux kernel for my processor should be configured with CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
Errata that is specific to implementation choices made during the design of this processor. - A LoadDoubleWord transaction to our 16550 Uart reg is UB, so we'll make it return what LoadByte would return. Really - any transaction against a Uart reg address larger than Byte e.g. LoadHalfWord or StoreHalfWord should return the same as the Byte transaction, but zero-padded. - any cache implementations must be aware of non-cacheable IO in machine mode - The Linux kernel for my processor should be configured with `CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS`
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Reference: Yehowshua/RiscV-Formal#7
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