diff --git a/hs/Decode.hs b/hs/Decode.hs
index 2411df3..49158de 100644
--- a/hs/Decode.hs
+++ b/hs/Decode.hs
@@ -158,6 +158,15 @@ decodeUType insn = case opcode of
     rd     = getRd     insn
     imm20  = getImm20UType insn
 
+getImm21JType :: Insn -> Unsigned 21
+getImm21JType instr = bitCoerce |> imm20 ++# imm10_1 ++# imm11 ++# imm19_12 ++# zero
+  where
+    imm20    = slice d31 d31 (pack instr)      -- imm[20]
+    imm10_1  = slice d30 d21 (pack instr)      -- imm[10:1]
+    imm11    = slice d20 d20 (pack instr)      -- imm[11]
+    imm19_12 = slice d19 d12 (pack instr)      -- imm[19:12]
+    zero     = 0 :: BitVector 1                -- LSB always zero for J-type
+
 decodeJType :: Insn -> Maybe Opcode
 decodeJType insn =
   case opcode of
@@ -168,15 +177,6 @@ decodeJType insn =
     rd     = getRd insn
     imm21  = getImm21JType insn
 
-getImm21JType :: Insn -> Unsigned 21
-getImm21JType instr = bitCoerce |> imm20 ++# imm10_1 ++# imm11 ++# imm19_12 ++# zero
-  where
-    imm20    = slice d31 d31 (pack instr)      -- imm[20]
-    imm10_1  = slice d30 d21 (pack instr)      -- imm[10:1]
-    imm11    = slice d20 d20 (pack instr)      -- imm[11]
-    imm19_12 = slice d19 d12 (pack instr)      -- imm[19:12]
-    zero     = 0 :: BitVector 1                -- LSB always zero for J-type
-
 getOpcode :: Insn -> Unsigned 7
 getOpcode instr = bitCoerce |> slice d6 d0 (pack instr)
 
diff --git a/hs/Execute.hs b/hs/Execute.hs
deleted file mode 100644
index dbeaf13..0000000
--- a/hs/Execute.hs
+++ /dev/null
@@ -1,6 +0,0 @@
-{-# LANGUAGE DataKinds #-}
-{-# LANGUAGE NumericUnderscores #-}
-
-module Execute(execute) where
-
-execute = 1
\ No newline at end of file
diff --git a/hs/Read.hs b/hs/Read.hs
deleted file mode 100644
index f1f9c2f..0000000
--- a/hs/Read.hs
+++ /dev/null
@@ -1,25 +0,0 @@
-{-# LANGUAGE DataKinds #-}
-{-# LANGUAGE NumericUnderscores #-}
-
-module Read(Read.read) where
-import Clash.Prelude
-import Types(DoubleWord, Addr)
-
-data RegVal = Value DoubleWord
-            | Borrowed
-            deriving (Generic, Show, Eq, NFDataX)
-
-data SRC = GPR RegVal
-         | FPR RegVal
-         | CSR RegVal
-         | PC  Addr
-         deriving (Generic, Show, Eq, NFDataX)
-
-data ReadResult = ReadResult
-  { src1 :: SRC,
-    src2 :: SRC,
-    src3 :: SRC
-  }
-  deriving (Generic, Show, Eq, NFDataX)
-
-read = 2
diff --git a/rv_formal.cabal b/rv_formal.cabal
index 6cddb3f..7422ea4 100644
--- a/rv_formal.cabal
+++ b/rv_formal.cabal
@@ -87,11 +87,8 @@ library
   exposed-modules:
     Simulation
   other-modules:
-    Fetch,
     Decode,
     DecodeTypes,
-    Execute,
-    Read,
     Peripherals.Ram,
     Peripherals.Uart,
     Peripherals.UartCFFI,
@@ -102,6 +99,7 @@ library
     BusTypes,
     Cpu,
     RegFiles,
+    Fetch,
     Exceptions,
     Util
   c-sources: c/uart_sim_device.c