commit ef58d5b07ee6b5a5112957b534757b237cfa8d7b Author: Yehowshua Immanuel Date: Wed Feb 12 23:54:15 2025 -0500 first commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..e28e10f --- /dev/null +++ b/.gitignore @@ -0,0 +1,227 @@ +stack.yaml.lock +src/Main +out/ +isa_json/ +odir/ +hidir/ +dist/ +dist-newstyle/ +.stack-work/ +cabal-dev +/cabal.project.local +.ghc.environment.* +*.o +*.o-boot +*.hi +*.hi-boot +*.po +*.po-boot +*.p_o +*.p_o-boot +*.chi +*.chs.h +*.dyn_o +*.dyn_o-boot +*.dyn_hi +*.dyn_hi-boot +.virtualenv +.hpc +.hsenv +.cabal-sandbox/ +cabal.sandbox.config +cabal.config +*.prof +*.aux +*.hp +*.bin +*.log +*.tar.gz + +*~ +*.DS_Store + +# IntelliJ +/.idea +*.iml + +# HDL directories often created during development cycle +/vhdl +/verilog +/systemverilog +.env +# Created by https://www.toptal.com/developers/gitignore/api/python +# Edit at https://www.toptal.com/developers/gitignore?templates=python + +### Python ### +# Byte-compiled / optimized / DLL files +__pycache__/ +*.py[cod] +*$py.class + +# C extensions +*.so + +# Distribution / packaging +.Python +build/ +develop-eggs/ +dist/ +downloads/ +eggs/ +.eggs/ +lib/ +lib64/ +parts/ +sdist/ +var/ +wheels/ +share/python-wheels/ +*.egg-info/ +.installed.cfg +*.egg +MANIFEST + +# PyInstaller +# Usually these files are written by a python script from a template +# before PyInstaller builds the exe, so as to inject date/other infos into it. +*.manifest +*.spec + +# Installer logs +pip-log.txt +pip-delete-this-directory.txt + +# Unit test / coverage reports +htmlcov/ +.tox/ +.nox/ +.coverage +.coverage.* +.cache +nosetests.xml +coverage.xml +*.cover +*.py,cover +.hypothesis/ +.pytest_cache/ +cover/ + +# Translations +*.mo +*.pot + +# Django stuff: +*.log +local_settings.py +db.sqlite3 +db.sqlite3-journal + +# Flask stuff: +instance/ +.webassets-cache + +# Scrapy stuff: +.scrapy + +# Sphinx documentation +docs/_build/ + +# PyBuilder +.pybuilder/ +target/ + +# Jupyter Notebook +.ipynb_checkpoints + +# IPython +profile_default/ +ipython_config.py + +# pyenv +# For a library or package, you might want to ignore these files since the code is +# intended to run in multiple environments; otherwise, check them in: +# .python-version + +# pipenv +# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control. +# However, in case of collaboration, if having platform-specific dependencies or dependencies +# having no cross-platform support, pipenv may install dependencies that don't work, or not +# install all needed dependencies. +#Pipfile.lock + +# poetry +# Similar to Pipfile.lock, it is generally recommended to include poetry.lock in version control. +# This is especially recommended for binary packages to ensure reproducibility, and is more +# commonly ignored for libraries. +# https://python-poetry.org/docs/basic-usage/#commit-your-poetrylock-file-to-version-control +#poetry.lock + +# pdm +# Similar to Pipfile.lock, it is generally recommended to include pdm.lock in version control. +#pdm.lock +# pdm stores project-wide configurations in .pdm.toml, but it is recommended to not include it +# in version control. +# https://pdm.fming.dev/#use-with-ide +.pdm.toml + +# PEP 582; used by e.g. github.com/David-OConnor/pyflow and github.com/pdm-project/pdm +__pypackages__/ + +# Celery stuff +celerybeat-schedule +celerybeat.pid + +# SageMath parsed files +*.sage.py + +# Environments +.env +.venv +env/ +venv/ +ENV/ +env.bak/ +venv.bak/ + +# Spyder project settings +.spyderproject +.spyproject + +# Rope project settings +.ropeproject + +# mkdocs documentation +/site + +# mypy +.mypy_cache/ +.dmypy.json +dmypy.json + +# Pyre type checker +.pyre/ + +# pytype static type analyzer +.pytype/ + +# Cython debug symbols +cython_debug/ + +# PyCharm +# JetBrains specific template is maintained in a separate JetBrains.gitignore that can +# be found at https://github.com/github/gitignore/blob/main/Global/JetBrains.gitignore +# and can be added to the global gitignore or merged into this file. For a more nuclear +# option (not recommended) you can uncomment the following to ignore the entire idea folder. +#.idea/ + +### Python Patch ### +# Poetry local configuration file - https://python-poetry.org/docs/configuration/#local-configuration +poetry.toml + +# ruff +.ruff_cache/ + +# LSP config files +pyrightconfig.json + +# End of https://www.toptal.com/developers/gitignore/api/python diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..19fac98 --- /dev/null +++ b/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2024 Yehowshua Immanuel + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/README.md b/README.md new file mode 100644 index 0000000..cf3b06c --- /dev/null +++ b/README.md @@ -0,0 +1,49 @@ +# About +An attempt at a formal reference model for the RISC-V ISA written in +Clash Haskell. + +# Getting Started +This works with ghc 9.4.8 + +The clash compiler is basically a modified version of ghc designed to allow for first class support of haskell code as circuits. + +Note that this repository is currently very much W.I.P. That being said, +this is how you would currently run a simulation: + +```bash +cabal run main --ghc-options="-D_RAM_DEPTH=2048" -- --firmware=./rv_tests/hello_world/hello.bin +``` + +# Notes +All the context that we pick up as we execute an instruction in +essence forms the context of our micro-op machinery. + +## Installing GCC-RISC-V Toolchain on [Insert Platform Here] + +Change instructions to support Nix + + +# TODO + - [ ] fetch should invoke mem read function + +# Organization Thoughts + - Potential functions + 1. BitPat -> Opcode + 2. Opcode -> Fields + 3. Fields -> Field Vals + 4. Field Vals -> Reg Vals + +# Thoroughness + - [ ] Check that all forms get used!! Remove unused forms!! + +# Grant Notes + - [ ] Some forms may be redundant(may need to remove some) + +## Quality of Life Enhancements + - [ ] turn off derive generics + - [ ] update commands to use flags that prevent ghc + intermediate outputs from littering source tree + - [ ] enable Phoityne debug + - [ ] learn to use trace and jupyter + - [ ] draw conclusions on feasibility of debugging + without VCD viewer diff --git a/Setup.hs b/Setup.hs new file mode 100644 index 0000000..470563e --- /dev/null +++ b/Setup.hs @@ -0,0 +1,5 @@ +import Prelude +import Distribution.Extra.Doctest (defaultMainWithDoctests) + +main :: IO () +main = defaultMainWithDoctests "doctests" diff --git a/bin/Clash.hs b/bin/Clash.hs new file mode 100644 index 0000000..7193d8b --- /dev/null +++ b/bin/Clash.hs @@ -0,0 +1,7 @@ + +import Prelude +import System.Environment (getArgs) +import Clash.Main (defaultMain) + +main :: IO () +main = getArgs >>= defaultMain diff --git a/bin/Clashi.hs b/bin/Clashi.hs new file mode 100644 index 0000000..227a201 --- /dev/null +++ b/bin/Clashi.hs @@ -0,0 +1,7 @@ + +import Prelude +import System.Environment (getArgs) +import Clash.Main (defaultMain) + +main :: IO () +main = getArgs >>= defaultMain . ("--interactive":) diff --git a/bin/Main.hs b/bin/Main.hs new file mode 100644 index 0000000..d0991b2 --- /dev/null +++ b/bin/Main.hs @@ -0,0 +1,46 @@ +{-# LANGUAGE GADTs #-} +{-# LANGUAGE DataKinds #-} +{-# LANGUAGE TypeOperators #-} +{-# LANGUAGE ConstraintKinds #-} + +module Main where + +import Prelude +import System.Environment (getArgs, getProgName) +import System.Exit (exitFailure) +import Data.Maybe (listToMaybe) +import Data.List (isPrefixOf) +import Text.Show.Pretty (ppShow) + +import Simulation (simulation, Args(..)) + +main :: IO () +main = do + rawArgs <- getArgs + args <- parseArgs rawArgs + states <- simulation args + putStrLn "Simulating Machine" + -- mapM_ (putStrLn . ppShow) states -- Uncomment to print each state, if needed. + putStrLn $ "Last state: " ++ show (last states) + putStrLn $ "Executed for " ++ show (length states) ++ " cycles" + putStrLn "Simulation complete" + +-- Function to parse command line arguments into the Args data type +parseArgs :: [String] -> IO Args +parseArgs argv = + case extractKey "firmware" argv of + Just firmwarePath -> return Args { firmware = firmwarePath } + Nothing -> do + progName <- getProgName + putStrLn "Error: No firmware file found." + putStrLn $ "Usage: " ++ progName ++ " --firmware=FILE" + exitFailure + +filterByKey :: String -> [String] -> [String] +filterByKey key argv = filter (switch `isPrefixOf`) argv + where + switch = "--" ++ key ++ "=" + +extractKey :: String -> [String] -> Maybe String +extractKey key argv = listToMaybe $ map removePrefix $ filterByKey key argv + where removePrefix = drop $ length ("--" ++ key ++ "=") diff --git a/c/uart_sim_device.c b/c/uart_sim_device.c new file mode 100644 index 0000000..524b8f7 --- /dev/null +++ b/c/uart_sim_device.c @@ -0,0 +1,74 @@ +#include +#include +#include +#include +#include +#include + +static volatile bool ctrl_c_received = false; + +void sigint_handler(int sig_num) { + ctrl_c_received = true; +} + +void setup_sigint_handler() { + signal(SIGINT, sigint_handler); +} + +bool was_ctrl_c_received() { + return ctrl_c_received; +} + +static struct termios oldt, newt; + +void init_terminal() { + // Get terminal attributes + tcgetattr(STDIN_FILENO, &oldt); + newt = oldt; + + // Set terminal to raw mode (no echo, non-canonical) + newt.c_lflag &= ~(ICANON | ECHO); + tcsetattr(STDIN_FILENO, TCSANOW, &newt); +} + +void restore_terminal() { + // Restore terminal to its old state + tcsetattr(STDIN_FILENO, TCSANOW, &oldt); +} + +char get_char_from_terminal() { + char c = getchar(); + return c; +} + +void write_char_to_terminal(char chr) { + putchar(chr); + fflush(stdout); +} + +int is_char_available() { + struct timeval tv; + fd_set read_fd_set; + + // Don't wait at all, not even a microsecond + tv.tv_sec = 0; + tv.tv_usec = 0; + + // Watch stdin (fd 0) to see when it has input + FD_ZERO(&read_fd_set); + FD_SET(0, &read_fd_set); + + // Check if there's any input available + if (select(1, &read_fd_set, NULL, NULL, &tv) == -1) { + perror("select"); + return 0; // 0 indicates no characters available + } + + if (FD_ISSET(0, &read_fd_set)) { + // Character is available + return 1; + } else { + // No character available + return 0; + } +} \ No newline at end of file diff --git a/cabal.project b/cabal.project new file mode 100644 index 0000000..255da59 --- /dev/null +++ b/cabal.project @@ -0,0 +1,16 @@ +packages: + rv_formal.cabal + +packages: . +builddir: build + +write-ghc-environment-files: always + +-- Eliminates the need for `--enable-tests`, which is needed for HLS. +tests: true + +-- Works around: https://github.com/recursion-schemes/recursion-schemes/issues/128. This +-- shouldn't harm (runtime) performance of Clash, as we only use recursion-schemes with +-- TemplateHaskell. +package recursion-schemes + optimization: 0 diff --git a/gen.sh b/gen.sh new file mode 100644 index 0000000..02e48f8 --- /dev/null +++ b/gen.sh @@ -0,0 +1,20 @@ +set -ex + +# dependencies +# TODO : re-enable the following +# python3 -m venv .env +# source .env/bin/activate +# pushd hs_gen +# pip3 install -r requirements.txt +# popd + +# generate +rm -rf out +mkdir -p out +python3 -m py.gen_json.gen_forms_and_field_mappings_json out +python3 -m py.gen_hs.extract_opcodes_to_haskell ./hs/Decode/Opcodes.hs +python3 -m py.gen_hs.extract_bitpat_to_haskell ./hs/Decode/BitpatsToOpcodes.hs +python3 -m py.gen_hs.generate_forms ./out/forms_v_fields.json ./hs/Decode/Forms.hs +python3 -m py.gen_hs.generate_fields ./out/field_v_slice.json ./hs/Decode/Fields.hs +python3 -m py.gen_hs.generate_opcodeToForms ./hs/Decode/OpcodeToForm.hs +python3 -m py.gen_hs.extract_fields ./out/field_v_slice.json ./hs/Decode/ExtractField.hs \ No newline at end of file diff --git a/hs/Decode/Opcodes.hs b/hs/Decode/Opcodes.hs new file mode 100644 index 0000000..6c48b4e --- /dev/null +++ b/hs/Decode/Opcodes.hs @@ -0,0 +1,52 @@ +{-# LANGUAGE DataKinds #-} +{-# LANGUAGE NumericUnderscores #-} + +module Decode.Opcodes(Opcode(..)) where +import Clash.Prelude +import Data.Functor.Contravariant (Op) + +type FUNCT7 = Unsigned 7 +type RS2 = Unsigned 5 +type RS1 = Unsigned 5 +type FUNCT3 = Unsigned 3 +type RD = Unsigned 5 +type OPCODE = Unsigned 7 + +type IMM12 = Unsigned 12 +type IMM13 = Unsigned 13 +type IMM20 = Unsigned 20 +type IMM21 = Unsigned 21 + +data RTypeFields = RTypeFields OPCODE RD FUNCT3 RS1 RS2 FUNCT7 +data ITypeFields = ITypeFields OPCODE RD FUNCT3 RS1 IMM12 +data STypeFields = STypeFields OPCODE FUNCT3 RS1 RS2 IMM12 +data BTypeFields = BTypeFields OPCODE FUNCT3 RS1 RS2 IMM13 +data UTypeFields = UTypeFields OPCODE RD IMM20 +data JTypeFields = JTypeFields OPCODE RD IMM21 + +data Opcode + = ADD RTypeFields + | SUB RTypeFields + | XOR RTypeFields + | OR RTypeFields + | AND RTypeFields + | SLL RTypeFields + | SRL RTypeFields + | SRA RTypeFields + | SLT RTypeFields + | SLTU RTypeFields + | ADDRI ITypeFields + | XORI ITypeFields + | ORI ITypeFields + | ANDI ITypeFields + | SLLI ITypeFields + | SRLI ITypeFields + | SRAI ITypeFields + | SLTI ITypeFields + | SLTIU ITypeFields + | LB ITypeFields + | LH ITypeFields + | LW ITypeFields + | LBU ITypeFields + | LHU ITypeFields + diff --git a/hs/Fetch.hs b/hs/Fetch.hs new file mode 100644 index 0000000..2bcc296 --- /dev/null +++ b/hs/Fetch.hs @@ -0,0 +1,24 @@ +{-# LANGUAGE DataKinds #-} +{-# LANGUAGE NumericUnderscores #-} + +module Fetch(fetchInstruction) where + +import Clash.Prelude +import Types(Mem, Addr, FullWord) +import Util(endianSwapWord) + +data Insn = Instruction FullWord + | Misaligned Addr + +fetchInstruction :: KnownNat n => Mem n -> Addr -> Insn +fetchInstruction mem addr = + let + isWordAligned = addr .&. 3 == 0 + addrWordAligned = addr `shiftR` 2 + insn = mem !! addrWordAligned + -- TODO : check if instruction is word aligned and create type + -- to capture if its not. + in + case isWordAligned of + True -> Instruction insn + False -> Misaligned addr diff --git a/hs/Machine.hs b/hs/Machine.hs new file mode 100644 index 0000000..4910422 --- /dev/null +++ b/hs/Machine.hs @@ -0,0 +1,67 @@ +{-# LANGUAGE DataKinds #-} +{-# LANGUAGE NumericUnderscores #-} + +module Machine( + Machine(..), + RISCVCPU(..), + Endian(..), + machineInit) where + +import Clash.Prelude +import Types(Pc, Mem) +import RegFiles(GPR, FPR, CSR, gprInit, fprInit, csrInit) + +data Endian = Big | Little + deriving (Generic, Show, Eq, NFDataX) + +data PrivilegeLevel + = MachineMode + | SuperVisorMode + | UserMode + deriving (Generic, Show, Eq, NFDataX) + +data RISCVCPU = RISCVCPU + { pc :: Pc, + gpr :: GPR, + fpr :: FPR, + privilegeLevel :: PrivilegeLevel + } + deriving (Generic, Show, Eq, NFDataX) + +data Machine = Machine + { cpu :: RISCVCPU, + mem :: Mem 14 + } + deriving (Generic, Show, Eq, NFDataX) + +riscvCPUInit :: RISCVCPU +riscvCPUInit = + RISCVCPU + 0 + gprInit + fprInit + MachineMode + +machineInit :: Machine +machineInit = + Machine + riscvCPUInit + memInit + +memInit :: Vec 14 (Unsigned 32) +memInit = + 0x0000A03C + :> 0x3000A5E8 + :> 0x1A002038 + :> 0x18002598 + :> 0x10002588 + :> 0x01002170 + :> 0xF8FF8141 + :> 0x08002588 + :> 0x01002138 + :> 0x00002598 + :> 0xE8FFFF4B + :> 0x00000060 + :> 0x002000C0 + :> 0x00000000 + :> Nil diff --git a/hs/Peripherals/Ram.hs b/hs/Peripherals/Ram.hs new file mode 100644 index 0000000..36d63dc --- /dev/null +++ b/hs/Peripherals/Ram.hs @@ -0,0 +1,93 @@ +{-# LANGUAGE ScopedTypeVariables #-} +{-# LANGUAGE CPP #-} +{-# LANGUAGE OverloadedStrings #-} +{-# LANGUAGE TemplateHaskell #-} + +module Peripherals.Ram() where + +import Clash.Prelude +import qualified Prelude as P +import qualified Data.ByteString.Lazy as BL +import Data.Binary.Get +import Data.Int (Int32) +import qualified Clash.Sized.Vector as Vec + +-- vector depth has to be known statically at compile time +#ifndef _RAM_DEPTH +#define _RAM_DEPTH 1024 +#endif + +-- TODO : replace Unsigned 32 with BusVal types later... +type Ram = Vec _RAM_DEPTH (Unsigned 32) + +initRamFromFile :: FilePath -> IO (Maybe Ram) +initRamFromFile filePath = + let + initRam = Vec.replicate (SNat :: SNat _RAM_DEPTH) 0 + in + do + bs <- readFileIntoByteString filePath + let ints = getInts bs + pure $ populateVectorFromInt32 ints initRam + +readFileIntoByteString :: FilePath -> IO BL.ByteString +readFileIntoByteString filePath = BL.readFile filePath + +-- Define a function to read a ByteString and convert to [Int32] +getInts :: BL.ByteString -> [Int32] +getInts bs = runGet listOfInts bs + where + listOfInts = do + empty <- isEmpty + if empty + then pure [] + else do + i <- getInt32le -- Parse a single Int32 from the stream + rest <- listOfInts -- Recursively parse the rest + pure (i : rest) + +-- Adjusts the length of a list of integers by either truncating or padding with zeros +populateVectorFromInt32 :: + KnownNat n => + [Int32] -> + Vec n (Unsigned 32) -> + Maybe (Vec n (Unsigned 32)) +populateVectorFromInt32 ls v = Vec.fromList adjustedLs + where + vecLen = length v + adjustedLs = fromIntegral <$> adjustLength vecLen ls + adjustLength :: Int -> [Int32] -> [Int32] + adjustLength n xs = P.take n (xs P.++ P.repeat 0) + + + +-- Function to increment each element of a Clash vector +-- prepareVector :: KnownNat n => [Int32] -> Vec n (Unsigned 32) +-- prepareVector xs = let +-- unsigneds = map (fromIntegral :: Int32 -> Unsigned 32) xs -- Step 1: Convert Int32 to Unsigned 32 +-- len = length unsigneds +-- in case compare len (snatToNum (SNat @n)) of -- Step 2: Adjust the length of the list +-- LT -> takeI unsigneds ++ repeat 0 -- Pad with zeros if the list is shorter +-- GT -> takeI unsigneds -- Truncate if the list is longer +-- EQ -> takeI unsigneds -- No padding or truncation needed + +-- Function to load firmware +-- loadFirmware :: KnownNat n => [Int32] -> Vec n (Unsigned 32) +-- loadFirmware (x:xs) = vecHead ++ vecTail +-- where +-- vecHead = singleton (fromIntegral x) +-- vecTail = loadFirmware xs +-- loadFirmware [] = takeI $ repeat 0 + +-- loadFirmware xs = v +-- where +-- mapped :: [Unsigned 32] = Clash.Prelude.fromIntegral <$> xs +-- c = takeI (mapped ++ repeat 0) +-- v = takeI $ (mapped ++ repeat 0) + +-- -- Example usage +-- someList :: [Int32] +-- someList = [1, 2, 3, 4, 5] + +-- mem :: Vec 16 (Unsigned 32) +-- mem = loadFirmware someList \ No newline at end of file diff --git a/hs/Peripherals/Setup.hs b/hs/Peripherals/Setup.hs new file mode 100644 index 0000000..a129587 --- /dev/null +++ b/hs/Peripherals/Setup.hs @@ -0,0 +1,8 @@ +module Peripherals.Setup (setupPeripherals) where + +import Prelude +import Peripherals.UartCFFI(initTerminal) + +setupPeripherals :: IO () +setupPeripherals = do + initTerminal \ No newline at end of file diff --git a/hs/Peripherals/Teardown.hs b/hs/Peripherals/Teardown.hs new file mode 100644 index 0000000..b70d5a3 --- /dev/null +++ b/hs/Peripherals/Teardown.hs @@ -0,0 +1,8 @@ +module Peripherals.Teardown(teardownPeripherals) where + +import Prelude +import Peripherals.UartCFFI(restoreTerminal) + +teardownPeripherals :: IO () +teardownPeripherals = do + restoreTerminal \ No newline at end of file diff --git a/hs/Peripherals/UartCFFI.hs b/hs/Peripherals/UartCFFI.hs new file mode 100644 index 0000000..b0998e9 --- /dev/null +++ b/hs/Peripherals/UartCFFI.hs @@ -0,0 +1,52 @@ +{-# LANGUAGE ForeignFunctionInterface #-} + +module Peripherals.UartCFFI ( + initTerminal, + restoreTerminal, + getCharFromTerminal, + writeCharToTerminal, + isCharAvailable, + setupSigintHandler, + wasCtrlCReceived +) where + +import Prelude +import Foreign.C.Types +import Foreign.C.String +import Foreign.Ptr +import Data.Char (chr, ord) + +-- Foreign imports directly corresponding to the C functions +foreign import ccall "init_terminal" c_initTerminal :: IO () +foreign import ccall "restore_terminal" c_restoreTerminal :: IO () +foreign import ccall "get_char_from_terminal" c_getCharFromTerminal :: IO CChar +foreign import ccall "write_char_to_terminal" c_writeCharToTerminal :: CChar -> IO () +foreign import ccall "is_char_available" c_isCharAvailable :: IO CInt +foreign import ccall "setup_sigint_handler" c_setupSigintHandler :: IO () +foreign import ccall "was_ctrl_c_received" c_wasCtrlCReceived :: IO CInt + +-- Haskell friendly wrappers +initTerminal :: IO () +initTerminal = c_initTerminal + +restoreTerminal :: IO () +restoreTerminal = c_restoreTerminal + +getCharFromTerminal :: IO Char +getCharFromTerminal = fmap (chr . fromEnum) c_getCharFromTerminal + +writeCharToTerminal :: Char -> IO () +writeCharToTerminal char = c_writeCharToTerminal (toEnum $ ord char) + +isCharAvailable :: IO Int +isCharAvailable = fmap fromEnum c_isCharAvailable + +setupSigintHandler :: IO () +setupSigintHandler = c_setupSigintHandler + +wasCtrlCReceived :: IO Int +wasCtrlCReceived = fmap fromEnum c_wasCtrlCReceived + +-- Improved version of the ctrlCReceived to use the new wasCtrlCReceived signature +ctrlCReceived :: IO Bool +ctrlCReceived = fmap (/= 0) wasCtrlCReceived \ No newline at end of file diff --git a/hs/RegFiles.hs b/hs/RegFiles.hs new file mode 100644 index 0000000..53386d3 --- /dev/null +++ b/hs/RegFiles.hs @@ -0,0 +1,56 @@ +{-# LANGUAGE DataKinds #-} +{-# LANGUAGE NumericUnderscores #-} + +module RegFiles( + GPR, + FPR, + CSR, + gprInit, + fprInit, + csrInit + ) where + +import Clash.Prelude + +-- In RISC-V, besides the GPR, FPR, and CSR, we may also encounter +-- the following which are not modeled in this codebase. +-- * VRF(Vector Registers File) for vector processing. +-- * Debug Registers (DBR) for hardware debugging. +-- * Shadow Registers for fast context switching (optional). +-- * MPU Registers for memory protection. +-- * Counter/Timer Registers for time/cycle counting. +-- * Hypervisor Registers (HPR) for guest virtualization. + +type GPR = Vec 32 (Unsigned 64) +type FPR = Vec 32 (Unsigned 64) +type CSR = Vec 4096 (Unsigned 64) + +gprInit :: GPR +gprInit = repeat 0 + +fprInit :: FPR +fprInit = repeat 0 + +-- TODO: CSR can't actually be all 0 during initialization. +-- We need to revisit the following and properly initialize +-- various registers later. +csrInit :: CSR +csrInit = + replace (0x301 :: Integer) misa_init + $ replace (0x300 :: Integer) mstatus_init + $ replace (0x305 :: Integer) mtvec_init + $ replace (0xF11 :: Integer) mvendorid_init + $ replace (0xF12 :: Integer) marchid_init + $ replace (0xF13 :: Integer) mimpid_init + $ replace (0x701 :: Integer) mtime_init + $ replace (0x321 :: Integer) mtimecmp_init + $ repeat 0 + where + misa_init = 0x8000000000001104 -- `RV64IMAFD` + mstatus_init = 0x0000000000001800 -- Default `mstatus` + mtvec_init = 0x0000000000001000 -- Trap vector base + mvendorid_init = 0x00000000 + marchid_init = 0x00000000 + mimpid_init = 0x00000000 + mtime_init = 0x0000000000000000 + mtimecmp_init = 0xFFFFFFFFFFFFFFFF diff --git a/hs/Simulation.hs b/hs/Simulation.hs new file mode 100644 index 0000000..023bc6e --- /dev/null +++ b/hs/Simulation.hs @@ -0,0 +1,71 @@ +{-# LANGUAGE GADTs #-} +{-# LANGUAGE DataKinds #-} +{-# LANGUAGE TypeOperators #-} +{-# LANGUAGE ConstraintKinds #-} + +module Simulation(Args(..), simulation) where + +import Peripherals.Setup(setupPeripherals) +import Peripherals.Teardown(teardownPeripherals) +import Text.Printf (printf) +import Clash.Prelude +import Machine( + Machine(..), + RISCVCPU(..), + machineInit, RISCVCPU (RISCVCPU)) +import Fetch(fetchInstruction) +import Peripherals.UartCFFI(writeCharToTerminal) +import Control.Concurrent (threadDelay) + +import Debug.Trace + +data Args = Args { + firmware :: FilePath + } deriving (Show) + +machine :: Machine +machine = machineInit + +machine' :: Machine -> Machine +machine' machine = + let + -- instruction = + -- traceShow + -- (printf "0x%X" (toInteger v) :: String) + -- v + -- where v = fetchInstruction mem msr pc + -- instruction = traceShow (bitpatToOpcode v) v + -- where v = fetchInstruction machineMem machinePC + machineMem = mem machine + machineCPU = cpu machine + machinePC = pc machineCPU + instruction = fetchInstruction machineMem machinePC + addr = 0 :: Integer + -- execute would go here, but right now, we simply + mem' = replace addr (3) machineMem + cpu' = machineCPU { pc = machinePC + 4 } + in + machine { cpu = cpu', mem = mem' } + +machineSignal :: HiddenClockResetEnable dom => Signal dom Machine +machineSignal = register machine (machine' <$> machineSignal) + +simulationLoop :: Int -> Machine -> IO [Machine] +simulationLoop 0 state = return [state] +simulationLoop n state = do + let newState = machine' state + rest <- simulationLoop (n - 1) newState + return (state : rest) + +simulation :: Args -> IO [Machine] +simulation args = do + setupPeripherals + + -- quick smoketest that UART works - remove later + writeCharToTerminal 'a' + threadDelay 1000000 -- Delay for 1 second (1,000,000 microseconds) + + let initState = machine + sim <- simulationLoop 5 initState + teardownPeripherals + return sim diff --git a/hs/Types.hs b/hs/Types.hs new file mode 100644 index 0000000..11300ee --- /dev/null +++ b/hs/Types.hs @@ -0,0 +1,24 @@ +{-# LANGUAGE DataKinds #-} +{-# LANGUAGE NumericUnderscores #-} + +module Types(Pc, BusVal(..), Mem, FullWord, Addr) where + +import Clash.Prelude + +type Byte = Unsigned 8 +type HalfWord = Unsigned 16 +type FullWord = Unsigned 32 +type DoubleWord = Unsigned 64 +type QuadWord = Unsigned 128 + +data BusVal + = BusByte Byte + | BusHalfWord HalfWord + | BusWord FullWord + | BusDoubleWord DoubleWord + | BusQuadWord QuadWord + deriving (Generic, Show, Eq, NFDataX) + +type Pc = DoubleWord +type Addr = DoubleWord +type Mem n = Vec n FullWord diff --git a/hs/Util.hs b/hs/Util.hs new file mode 100644 index 0000000..cfd3924 --- /dev/null +++ b/hs/Util.hs @@ -0,0 +1,44 @@ +{-# LANGUAGE GADTs #-} +{-# LANGUAGE DataKinds #-} +{-# LANGUAGE TypeOperators #-} +{-# LANGUAGE ConstraintKinds #-} + +module Util( + powerIndex32, + powerIndex64, + endianSwapWord) where + +import Clash.Prelude +import Types(FullWord) + +data ValidIndex32 (n :: Nat) where + ValidIndex32 :: (0 <= n, n <= 31) => SNat n -> ValidIndex32 n + +mkValidIndex32 :: forall n. (KnownNat n, 0 <= n, n <= 31) => ValidIndex32 n +mkValidIndex32 = ValidIndex32 $ SNat @n + +powerIndex32 :: forall n. (KnownNat n, 0 <= n, n <= 31) => SNat (31 - n) +powerIndex32 = case mkValidIndex32 @n of + ValidIndex32 _ -> SNat @(31 - n) + +data ValidIndex63 (n :: Nat) where + ValidIndex63 :: (0 <= n, n <= 63) => SNat n -> ValidIndex63 n + +mkValidIndex64 :: forall n. (KnownNat n, 0 <= n, n <= 63) => ValidIndex63 n +mkValidIndex64 = ValidIndex63 $ SNat @n + +powerIndex64 :: forall n. (KnownNat n, 0 <= n, n <= 63) => SNat (63 - n) +powerIndex64 = case mkValidIndex64 @n of + ValidIndex63 _ -> SNat @(63 - n) + +endianSwapWord :: FullWord -> FullWord +endianSwapWord x = + (byte0 `shiftL` 24) .|. + (byte1 `shiftL` 16) .|. + (byte2 `shiftL` 8) .|. + byte3 + where + byte0 = (x .&. 0x000000FF) + byte1 = (x .&. 0x0000FF00) `shiftR` 8 + byte2 = (x .&. 0x00FF0000) `shiftR` 16 + byte3 = (x .&. 0xFF000000) `shiftR` 24 \ No newline at end of file diff --git a/rv_formal.cabal b/rv_formal.cabal new file mode 100644 index 0000000..f8ed3bd --- /dev/null +++ b/rv_formal.cabal @@ -0,0 +1,132 @@ +cabal-version: 2.4 +name: rvFormal +version: 0.1 +license: BSD-2-Clause +author: John Smith +maintainer: John Smith + +common common-options + default-extensions: + NumericUnderscores + DeriveDataTypeable + BangPatterns + BinaryLiterals + ConstraintKinds + DataKinds + DefaultSignatures + DeriveAnyClass + DeriveDataTypeable + DeriveFoldable + DeriveFunctor + DeriveGeneric + DeriveLift + DeriveTraversable + DerivingStrategies + InstanceSigs + KindSignatures + LambdaCase + NoStarIsType + PolyKinds + RankNTypes + ScopedTypeVariables + StandaloneDeriving + TupleSections + TypeApplications + TypeFamilies + TypeOperators + ViewPatterns + FlexibleContexts + MagicHash + + -- TemplateHaskell is used to support convenience functions such as + -- 'listToVecTH' and 'bLit'. + TemplateHaskell + QuasiQuotes + + -- Prelude isn't imported by default as Clash offers Clash.Prelude + NoImplicitPrelude + ghc-options: + -Wall -Wcompat + -haddock + + -- Plugins to support type-level constraint solving on naturals + -fplugin GHC.TypeLits.Extra.Solver + -fplugin GHC.TypeLits.Normalise + -fplugin GHC.TypeLits.KnownNat.Solver + + -- Clash needs access to the source code in compiled modules + -fexpose-all-unfoldings + + -- Worker wrappers introduce unstable names for functions that might have + -- blackboxes attached for them. You can disable this, but be sure to add + -- a no-specialize pragma to every function with a blackbox. + -fno-worker-wrapper + build-depends: + base, + Cabal, + + -- clash-prelude will set suitable version bounds for the plugins + clash-prelude >= 1.6.4 && < 1.10, + ghc-typelits-natnormalise, + ghc-typelits-extra, + ghc-typelits-knownnat, + binary, + bytestring, + mtl, + pretty-show + +custom-setup + setup-depends: + base >= 4.11, + Cabal >= 2.4, + cabal-doctest >= 1.0.1 && <1.1 + +library + import: common-options + hs-source-dirs: hs + exposed-modules: + Simulation + other-modules: + Decode.Opcodes, + Peripherals.Ram, + Peripherals.UartCFFI, + Peripherals.Setup, + Peripherals.Teardown, + Types, + Machine, + RegFiles, + Fetch, + Util + c-sources: c/uart_sim_device.c + include-dirs: c + default-language: Haskell2010 + +-- Builds the executable 'clash', with rvFormal project in scope +executable clash + main-is: bin/Clash.hs + default-language: Haskell2010 + Build-Depends: base, clash-ghc, rvFormal + if !os(Windows) + ghc-options: -dynamic + +-- Builds the executable 'clashi', with rvFormal project in scope +executable clashi + main-is: bin/Clashi.hs + default-language: Haskell2010 + if !os(Windows) + ghc-options: -dynamic + build-depends: base, clash-ghc, rvFormal + +executable main + import: common-options + main-is: bin/Main.hs + -- hs-source-dirs: hs + default-language: Haskell2010 + build-depends: + base, + clash-ghc, + rvFormal + c-sources: c/uart_sim_device.c + include-dirs: c + if !os(Windows) + ghc-options: -dynamic diff --git a/rv_tests/hello_world/Makefile b/rv_tests/hello_world/Makefile new file mode 100644 index 0000000..1d021ae --- /dev/null +++ b/rv_tests/hello_world/Makefile @@ -0,0 +1,37 @@ +# RISC-V toolchain +CC = riscv64-unknown-elf-gcc +AS = riscv64-unknown-elf-as +LD = riscv64-unknown-elf-ld +OBJCOPY = riscv64-unknown-elf-objcopy +QEMU = qemu-system-riscv64 + +# Compilation flags +ARCH_FLAGS = -march=rv64imac -mabi=lp64 +LDSCRIPT = linker.ld + +# Output files +ELF = hello.elf +BIN = hello.bin +OBJ = hello.o +SRC = hello.S + +# Default rule +all: $(BIN) + +# Assemble and link to ELF +$(ELF): $(SRC) $(LDSCRIPT) + $(AS) $(ARCH_FLAGS) -o $(OBJ) $(SRC) + $(LD) -T $(LDSCRIPT) -o $(ELF) $(OBJ) + +# Convert ELF to raw binary +$(BIN): $(ELF) + $(OBJCOPY) -O binary $(ELF) $(BIN) + +# Run in QEMU +run: $(BIN) + echo "Press CTRL+A then X to exit QEMU" + $(QEMU) -machine virt -nographic -bios none -kernel $(BIN) -device loader,file=$(BIN),addr=0x80000000 + +# Clean up generated files +clean: + rm -f $(OBJ) $(ELF) $(BIN) diff --git a/rv_tests/hello_world/build.sh b/rv_tests/hello_world/build.sh new file mode 100644 index 0000000..3990d80 --- /dev/null +++ b/rv_tests/hello_world/build.sh @@ -0,0 +1,8 @@ +# Assemble the code +riscv64-unknown-elf-as -march=rv64imac -mabi=lp64 -o hello.o hello.S + +# Link with our linker script to create an ELF file +riscv64-unknown-elf-ld -T linker.ld -o hello.elf hello.o + +# Convert ELF to a raw binary +riscv64-unknown-elf-objcopy -O binary hello.elf hello.bin diff --git a/rv_tests/hello_world/hello.S b/rv_tests/hello_world/hello.S new file mode 100644 index 0000000..ffef385 --- /dev/null +++ b/rv_tests/hello_world/hello.S @@ -0,0 +1,23 @@ +.section .text.init +.global _start + +.equ UART_BASE, 0x10000000 # QEMU's UART base address + +_start: + # Load address of the string into a1 + la a1, message + +loop: + lbu a0, 0(a1) # Load a byte from the string + beqz a0, exit # If null terminator, exit + li t0, UART_BASE # Load UART address + sb a0, 0(t0) # Store character to UART (8-bit write) + addi a1, a1, 1 # Move to next character + j loop # Repeat + +exit: + j exit # Infinite loop + +.section .rodata +message: + .asciz "Hello, world!\n" diff --git a/rv_tests/hello_world/hello.elf b/rv_tests/hello_world/hello.elf new file mode 100755 index 0000000..3994604 Binary files /dev/null and b/rv_tests/hello_world/hello.elf differ diff --git a/rv_tests/hello_world/linker.ld b/rv_tests/hello_world/linker.ld new file mode 100644 index 0000000..49e379f --- /dev/null +++ b/rv_tests/hello_world/linker.ld @@ -0,0 +1,25 @@ +OUTPUT_ARCH(riscv) +ENTRY(_start) + +SECTIONS +{ + /* Start execution at 0x80000000 */ + . = 0x80000000; + + .text : { + *(.text.init) + *(.text) + } + + .rodata : { + *(.rodata) + } + + .data : { + *(.data) + } + + .bss : { + *(.bss) + } +} diff --git a/shell.nix b/shell.nix new file mode 100644 index 0000000..fb93d74 --- /dev/null +++ b/shell.nix @@ -0,0 +1,16 @@ +{ pkgs ? import {} }: + +let + riscv64-linux = pkgs.pkgsCross.riscv64; +in +pkgs.mkShell { + buildInputs = [ + riscv64-linux.gcc + riscv64-linux.binutils + riscv64-linux.glibc + ]; + + shellHook = '' + echo "RISC-V Linux cross-compilation environment initialized!" + ''; +} \ No newline at end of file diff --git a/stack.yaml b/stack.yaml new file mode 100644 index 0000000..cb1198d --- /dev/null +++ b/stack.yaml @@ -0,0 +1,10 @@ +resolver: lts-21.20 + +extra-deps: + - GenericPretty-1.2.2 + - clash-ghc-1.8.1 + - clash-prelude-1.8.1 + - clash-lib-1.8.1 + - concurrent-supply-0.1.8 + - prettyprinter-interp-0.2.0.0 + - pretty-show-1.10 diff --git a/tables/instruction_forms.xlsx b/tables/instruction_forms.xlsx new file mode 100644 index 0000000..537f920 Binary files /dev/null and b/tables/instruction_forms.xlsx differ diff --git a/tables/isa.csv b/tables/isa.csv new file mode 100644 index 0000000..b120069 --- /dev/null +++ b/tables/isa.csv @@ -0,0 +1,934 @@ +,Mnemonic,PAGE,bitpat,FORMAT,FORMAT_OLD,SRC1,SRC2,SRC3,SRC4,SRC5,DEST1,DEST2,DEST3,DEST4,DEST5,Special Behavior,"Context +Synchronizing?",BOOK,Versions,Priveledge,Mode Dep,Name,Unsure,"Doable but +Laborious",MicroWatt Support,PythonWatt Support,MicroPython +0,fmadd[.],157,111111 ..... ..... ..... ..... 11101.,A4,A,,FPR,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,P1,,,Floating Multiply-Add,,,,, +1,fmadds[.],157,111011 ..... ..... ..... ..... 11101.,A4,A,,FPR,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,PPC,,,Floating Multiply-Add Single,,,,, +2,fmsub[.],158,111111 ..... ..... ..... ..... 11100.,A4,A,,FPR,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,P1,,,Floating Multiply-Subtract,,,,, +3,fmsubs[.],158,111011 ..... ..... ..... ..... 11100.,A4,A,,FPR,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,PPC,,,Floating Multiply-Subtract Single,,,,, +4,fnmadd[.],158,111111 ..... ..... ..... ..... 11111.,A4,A,,FPR,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,P1,,,Floating Negative Multiply-Add,,,,, +5,fnmadds[.],158,111011 ..... ..... ..... ..... 11111.,A4,A,,FPR,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,PPC,,,Floating Negative Multiply-Add Single,,,,, +6,fnmsub[.],158,111111 ..... ..... ..... ..... 11110.,A4,A,,FPR,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,P1,,,Floating Negative Multiply-Subtract,,,,,Y +7,fnmsubs[.],158,111011 ..... ..... ..... ..... 11110.,A4,A,,FPR,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,PPC,,,Floating Negative Multiply-Subtract Single,,,,, +8,dadd[.],193,111011 ..... ..... ..... 00000 00010.,X44,X,,,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,v2.05,,,DFP Add,,,,, +9,dcffix[.],215,111011 ..... ///// ..... 11001 00010.,X36,X,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.06,,,DFP Convert From Fixed,,,,, +10,dctdp[.],213,111011 ..... ///// ..... 01000 00010.,X36,X,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.05,,,DFP Convert To DFP Long,,,,, +11,dctfix[.],215,111011 ..... ///// ..... 01001 00010.,X36,X,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.05,,,DFP Convert To Fixed,,,,, +12,dctfixq[.],215,111111 ..... ///// ..... 01001 00010.,X37,X,,,FPR,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.05,,,DFP Convert To Fixed Quad,,,,, +13,ddiv[.],196,111011 ..... ..... ..... 10001 00010.,X44,X,,,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,v2.05,,,DFP Divide,,X,,, +14,denbcd[.],217,111011 ..... .//// ..... 11010 00010.,X46,X,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.05,,,DFP Encode BCD To DPD,,,,, +15,dmul[.],195,111011 ..... ..... ..... 00001 00010.,X44,X,,,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,v2.05,,,DFP Multiply,,,,, +16,dqua[.],204,111011 ..... ..... ..... ..000 00011.,Z23_2,Z23,,,FPR,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.05,,,DFP Quantize,,,,, +17,dquai[.],203,111011 ..... ..... ..... ..010 00011.,Z23_3,Z23,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.05,,,DFP Quantize Immediate,,,,, +18,drintn[.],211,111011 ..... ////. ..... ..111 00011.,Z23_1,Z23,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.05,,,DFP Round To FP Integer Without Inexact,,,,, +19,drintx[.],209,111011 ..... ////. ..... ..011 00011.,Z23_1,Z23,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.05,,,DFP Round To FP Integer With Inexact,,,,, +20,drrnd[.],206,111011 ..... ..... ..... ..001 00011.,Z23_2,Z23,,,FPR,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.05,,,DFP Reround,,,,, +21,drsp[.],214,111011 ..... ///// ..... 11000 00010.,X36,X,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.05,,,DFP Round To DFP Short,,,,, +22,dsub[.],193,111011 ..... ..... ..... 10000 00010.,X44,X,,,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,v2.05,,,DFP Subtract,,,,, +23,fadd[.],152,111111 ..... ..... ..... ///// 10101.,A3,A,,,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,P1,,,Floating Add,,,,, +24,fadds[.],152,111011 ..... ..... ..... ///// 10101.,A3,A,,,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,PPC,,,Floating Add Single,,,,, +25,fcfid[.],163,111111 ..... ///// ..... 11010 01110.,X36,X,,,,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,PPC,,,Floating Convert with round Signed Doubleword to Double-Precision format,,,,, +26,fcfids[.],164,111011 ..... ///// ..... 11010 01110.,X36,X,,,,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,v2.06,,,Floating Convert with round Signed Doubleword to Single-Precision format,,,,, +27,fcfidu[.],164,111111 ..... ///// ..... 11110 01110.,X36,X,,,,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,v2.06,,,Floating Convert with round Unsigned Doubleword to Double-Precision format,,,,, +28,fcfidus[.],165,111011 ..... ///// ..... 11110 01110.,X36,X,,,,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,v2.06,,,Floating Convert with round Unsigned Doubleword to Single-Precision format,,,,, +29,fctid[.],159,111111 ..... ///// ..... 11001 01110.,X36,X,,,,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,PPC,,,Floating Convert with round Double-Precision To Signed Doubleword format,,,,, +30,fctidu[.],160,111111 ..... ///// ..... 11101 01110.,X36,X,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.06,,,Floating Convert with round Double-Precision To Unsigned Doubleword format,,,,, +31,fctiduz[.],161,111111 ..... ///// ..... 11101 01111.,X36,X,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.06,,,Floating Convert with round to Zero Double-Precision To Unsigned Doubleword format,,,,, +32,fctidz[.],160,111111 ..... ///// ..... 11001 01111.,X36,X,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,PPC,,,Floating Convert with round to Zero Double-Precision To Signed Doubleword format,,,,, +33,fctiw[.],161,111111 ..... ///// ..... 00000 01110.,X36,X,,,,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,P2,,,Floating Convert with round Double-Precision To Signed Word format,,,,, +34,fctiwu[.],162,111111 ..... ///// ..... 00100 01110.,X36,X,,,,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,v2.06,,,Floating Convert with round Double-Precision To Unsigned Word format,,,,, +35,fctiwuz[.],163,111111 ..... ///// ..... 00100 01111.,X36,X,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.06,,,Floating Convert with round to Zero Double-Precision To Unsigned Word format,,,,, +36,fctiwz[.],162,111111 ..... ///// ..... 00000 01111.,X36,X,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,P2,,,Floating Convert with round to Zero Double-Precision To Signed Word format,,,,, +37,fdiv[.],153,111111 ..... ..... ..... ///// 10010.,A3,A,,,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,P1,,,Floating Divide,,X,,, +38,fdivs[.],153,111011 ..... ..... ..... ///// 10010.,A3,A,,,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,PPC,,,Floating Divide Single,,X,,, +39,fmul[.],153,111111 ..... ..... ///// ..... 11001.,A2,A,,,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,P1,,,Floating Multiply,,,,, +40,fre[.],154,111111 ..... ///// ..... ///// 11000.,A1,A,,,,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,v2.02,,,Floating Reciprocal Estimate,,,,, +41,fres[.],154,111011 ..... ///// ..... ///// 11000.,A1,A,,,,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,PPC,,,Floating Reciprocal Estimate Single,,,,, +42,frim[.],166,111111 ..... ///// ..... 01111 01000.,X36,X,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.02,,,Floating Round To Integer Minus,,,,, +43,frin[.],166,111111 ..... ///// ..... 01100 01000.,X36,X,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.02,,,Floating Round To Integer Nearest,,,,, +44,frip[.],166,111111 ..... ///// ..... 01110 01000.,X36,X,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.02,,,Floating Round To Integer Plus,,,,, +45,friz[.],166,111111 ..... ///// ..... 01101 01000.,X36,X,,,,FPR,,FPR,FPSCR,FPSCR,CR1,,,,I,v2.02,,,Floating Round To Integer Zero,,,,, +46,frsp[.],159,111111 ..... ///// ..... 00000 01100.,X36,X,,,,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,P1,,,Floating Round to Single-Precision,,,,, +47,frsqrte[.],155,111111 ..... ///// ..... ///// 11010.,A1,A,,,,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,PPC,,,Floating Reciprocal Square Root Estimate,,,,, +48,frsqrtes[.],155,111011 ..... ///// ..... ///// 11010.,A1,A,,,,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,v2.02,,,Floating Reciprocal Square Root Estimate Single,,,,, +49,fsqrt[.],154,111111 ..... ///// ..... ///// 10110.,A1,A,,,,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,P2,,,Floating Square Root,,,,, +50,fsqrts[.],154,111011 ..... ///// ..... ///// 10110.,A1,A,,,,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,PPC,,,Floating Square Root Single,,,,, +51,fsub[.],152,111111 ..... ..... ..... ///// 10100.,A3,A,,,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,P1,,,Floating Subtract,,,,, +52,fsubs[.],152,111011 ..... ..... ..... ///// 10100.,A3,A,,,FPR,FPR,FPSCR,FPR,FPSCR,FPSCR,CR1,,,,I,PPC,,,Floating Subtract Single,,,,, +53,daddq[.],193,111111 ..... ..... ..... 00000 00010.,X51,X,FPR,FPR,FPR,FPR,FPSCR,FPR,FPR,FPSCR,FPSCR,CR1,,,I,v2.05,,,DFP Add Quad,,,,, +54,ddivq[.],196,111111 ..... ..... ..... 10001 00010.,X51,X,FPR,FPR,FPR,FPR,FPSCR,FPR,FPR,FPSCR,FPSCR,CR1,,,I,v2.05,,,DFP Divide Quad,,X,,, +55,dmulq[.],195,111111 ..... ..... ..... 00001 00010.,X51,X,FPR,FPR,FPR,FPR,FPSCR,FPR,FPR,FPSCR,FPSCR,CR1,,,I,v2.05,,,DFP Multiply Quad,,,,, +56,dsubq[.],193,111111 ..... ..... ..... 10000 00010.,X51,X,FPR,FPR,FPR,FPR,FPSCR,FPR,FPR,FPSCR,FPSCR,CR1,,,I,v2.05,,,DFP Subtract Quad,,,,, +57,dquaq[.],204,111111 ..... ..... ..... ..000 00011.,Z23_6,Z23,FPR,FPR,FPR,FPR,,FPR,FPR,FPSCR,FPSCR,CR1,,,I,v2.05,,,DFP Quantize Quad,,,,, +58,dcffixq[.],215,111111 ..... ///// ..... 11001 00010.,X48,X,,,,FPR,,FPR,FPR,FPSCR,FPSCR,CR1,,,I,v2.05,,,DFP Convert From Fixed Quad,,,,, +59,dctqpq[.],213,111111 ..... ///// ..... 01000 00010.,X48,X,,,,FPR,,FPR,FPR,FPSCR,FPSCR,CR1,,,I,v2.05,,,DFP Convert To DFP Extended,,,,, +60,denbcdq[.],217,111111 ..... .//// ..... 11010 00010.,X53,X,,,FPR,FPR,,FPR,FPR,FPSCR,FPSCR,CR1,,,I,v2.05,,,DFP Encode BCD To DPD Quad,,,,, +61,dquaiq[.],203,111111 ..... ..... ..... ..010 00011.,Z23_7,Z23,,,FPR,FPR,,FPR,FPR,FPSCR,FPSCR,CR1,,,I,v2.05,,,DFP Quantize Immediate Quad,,,,, +62,drdpq[.],214,111111 ..... ///// ..... 11000 00010.,X49,X,,,FPR,FPR,,FPR,FPR,FPSCR,FPSCR,CR1,,,I,v2.05,,,DFP Round To DFP Long,,,,, +63,drintnq[.],211,111111 ..... ////. ..... ..111 00011.,Z23_4,Z23,,,FPR,FPR,,FPR,FPR,FPSCR,FPSCR,CR1,,,I,v2.05,,,DFP Round To FP Integer Without Inexact Quad,,,,, +64,drintxq[.],209,111111 ..... ////. ..... ..011 00011.,Z23_4,Z23,,,FPR,FPR,,FPR,FPR,FPSCR,FPSCR,CR1,,,I,v2.05,,,DFP Round To FP Integer With Inexact Quad,,,,, +65,drrndq[.],206,111111 ..... ..... ..... ..001 00011.,Z23_5,Z23,,FPR,FPR,FPR,,FPR,FPR,FPSCR,FPSCR,CR1,,,I,v2.05,,,DFP Reround Quad,,,,, +66,tbegin.,890,011111 .///. ///// ///// 10100 011101,X17,X,,MSR,CIA,SPR,SPR,CR,SPR,SPR,MSR,,,,II,v2.07,,,Transaction Begin & record,X,,,, +67,tabortdc.,894,011111 ..... ..... ..... 11001 011101,X88,X,,MSR,GPR,GPR,SPR,CR,SPR,SPR,MSR,,,,II,v2.07,,,Transaction Abort Doubleword Conditional & record,X,,,, +68,tabortwc.,893,011111 ..... ..... ..... 11000 011101,X88,X,,MSR,GPR,GPR,SPR,CR,SPR,SPR,MSR,,,,II,v2.07,,,Transaction Abort Word Conditional & record,X,,,, +69,tabort.,892,011111 ///// ..... ///// 11100 011101,X5,X,,,,GPR,MSR,CR,SPR,SPR,MSR,,,,II,v2.07,,,Transaction Abort & record,X,,,, +70,tabortdci.,894,011111 ..... ..... ..... 11011 011101,X86,X,,,GPR,SPR,MSR,CR,SPR,SPR,MSR,,,,II,v2.07,,,Transaction Abort Doubleword Conditional Immediate & record,X,,,, +71,tabortwci.,893,011111 ..... ..... ..... 11010 011101,X86,X,,,GPR,SPR,MSR,CR,SPR,SPR,MSR,,,,II,v2.07,,,Transaction Abort Word Conditional Immediate & record,X,,,, +72,treclaim.,969,011111 ///// ..... ///// 11101 011101,X5,X,,,GPR,SPR,MSR,CR,SPR,SPR,MSR,,,,II,v2.07,,,Transaction Reclaim & record,X,,,, +73,sc,42,010001 ///// ///// ////. ..... .///1/,SC1,SC,,,,CIA,MSR,SPR,SPR,MSR,NIA,,"system-service dependent, and also hypervisor-mode dependent",Y,I,PPC,,,System Call,X,,Y,, +74,scv,42,010001 ///// ///// ////. ..... .///01,SC1,SC,,,,CIA,MSR,SPR,LR,MSR,NIA,,"system-service dependent, and also hypervisor-mode dependent",Y,I,v3.0,,,System Call Vectored,X,,,, +75,mtspr,117 974,011111 ..... ..... ..... 01110 10011/,XFX4,X,AMOR,PATE,GPR,SPR,MSR,SPR*,,,,,architecture/implementation-specific behavior,,X,P1,O,,Move To SPR,,,Y,, +76,dcmpoq,199,111111 ...// ..... ..... 00100 00010/,X23,X,FPR,FPR,FPR,FPR,,CR,FPSCR,FPSCR,,,,,I,v2.05,,,DFP Compare Ordered Quad,,,,, +77,dcmpuq,198,111111 ...// ..... ..... 10100 00010/,X23,X,FPR,FPR,FPR,FPR,,CR,FPSCR,FPSCR,,,,,I,v2.05,,,DFP Compare Unordered Quad,,,,, +78,dtstexq,201,111111 ...// ..... ..... 00101 00010/,X23,X,FPR,FPR,FPR,FPR,,CR,FPSCR,,,,,,I,v2.05,,,DFP Test Exponent Quad,,,,, +79,stfdpx,149,011111 ..... ..... ..... 11100 10111/,X34,X,FPR,FPR,GPR,GPR,,,,,,,,,I,v2.05,,,Store Floating Double Pair Indexed,,,,, +80,xsaddqp[o],520,111111 ..... ..... ..... 00000 00100.,X94,X,,VSR,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Add Quad-Precision [with round to Odd],,,,, +81,xscmpeqdp,524,111100 ..... ..... ..... 00000 011...,XX3_5,XX3,,VSR,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Compare Equal Double-Precision,,,,, +82,xscmpgedp,525,111100 ..... ..... ..... 00010 011...,XX3_5,XX3,,VSR,VSR,FPSCR,MSR,VSR,FPSCR,,,,,,I,v3.0,,,VSX Scalar Compare Greater Than or Equal Double-Precision,,,,, +83,xscmpgtdp,526,111100 ..... ..... ..... 00001 011...,XX3_5,XX3,,VSR,VSR,FPSCR,MSR,VSR,FPSCR,,,,,,I,v3.0,,,VSX Scalar Compare Greater Than Double-Precision,,,,, +84,xscmpoqp,529,111111 ...// ..... ..... 00100 00100/,X28,X,,VSR,VSR,FPSCR,MSR,CR,FPSCR,,,,,,I,v3.0,,,VSX Scalar Compare Ordered Quad-Precision,,,,, +85,xsdivqp[o],564,111111 ..... ..... ..... 10001 00100.,X94,X,,VSR,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Divide Quad-Precision [with round to Odd],,X,,, +86,xsmaddadp,570,111100 ..... ..... ..... 00100 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Multiply-Add Type-A Double-Precision,,,,, +87,xsmaddasp,573,111100 ..... ..... ..... 00000 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Multiply-Add Type-A Single-Precision,,,,, +88,xsmaddmdp,570,111100 ..... ..... ..... 00101 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Multiply-Add Type-M Double-Precision,,,,, +89,xsmaddmsp,573,111100 ..... ..... ..... 00001 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Multiply-Add Type-M Single-Precision,,,,, +90,xsmaxcdp,581,111100 ..... ..... ..... 10000 000...,XX3_5,XX3,,VSR,VSR,FPSCR,MSR,VSR,FPSCR,,,,,,I,v3.0,,,VSX Scalar Maximum Type-C Double-Precision,,,,, +91,xsmaxjdp,583,111100 ..... ..... ..... 10010 000...,XX3_5,XX3,,VSR,VSR,FPSCR,MSR,VSR,FPSCR,,,,,,I,v3.0,,,VSX Scalar Maximum Type-J Double-Precision,,,,, +92,xsmincdp,587,111100 ..... ..... ..... 10001 000...,XX3_5,XX3,,VSR,VSR,FPSCR,MSR,VSR,FPSCR,,,,,,I,v3.0,,,VSX Scalar Minimum Type-C Double-Precision,,,,, +93,xsminjdp,589,111100 ..... ..... ..... 10011 000...,XX3_5,XX3,,VSR,VSR,FPSCR,MSR,VSR,FPSCR,,,,,,I,v3.0,,,VSX Scalar Minimum Type-J Double-Precision,,,,, +94,xsmsubadp,591,111100 ..... ..... ..... 00110 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Multiply-Subtract Type-A Double-Precision,,,,, +95,xsmsubasp,594,111100 ..... ..... ..... 00010 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Multiply-Subtract Type-A Single-Precision,,,,, +96,xsmsubmdp,591,111100 ..... ..... ..... 00111 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Multiply-Subtract Type-M Double-Precision,,,,, +97,xsmsubmsp,594,111100 ..... ..... ..... 00011 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Multiply-Subtract Type-M Single-Precision,,,,, +98,xsmulqp[o],602,111111 ..... ..... ..... 00001 00100.,X94,X,,VSR,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Multiply Quad-Precision [with round to Odd],,,,, +99,xsnmaddadp,608,111100 ..... ..... ..... 10100 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Negative Multiply-Add Type-A Double-Precision,,,,, +100,xsnmaddasp,613,111100 ..... ..... ..... 10000 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Negative Multiply-Add Type-A Single-Precision,,,,, +101,xsnmaddmdp,608,111100 ..... ..... ..... 10101 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Negative Multiply-Add Type-M Double-Precision,,,,, +102,xsnmaddmsp,613,111100 ..... ..... ..... 10001 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Negative Multiply-Add Type-M Single-Precision,,,,, +103,xsnmsubadp,619,111100 ..... ..... ..... 10110 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Negative Multiply-Subtract Type-A Double-Precision,,,,, +104,xsnmsubasp,622,111100 ..... ..... ..... 10010 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Negative Multiply-Subtract Type-A Single-Precision,,,,, +105,xsnmsubmdp,619,111100 ..... ..... ..... 10111 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Negative Multiply-Subtract Type-M Double-Precision,,,,, +106,xsnmsubmsp,622,111100 ..... ..... ..... 10011 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Negative Multiply-Subtract Type-M Single-Precision,,,,, +107,xssubqp[o],647,111111 ..... ..... ..... 10000 00100.,X94,X,,VSR,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Subtract Quad-Precision [with round to Odd],,,,, +108,xvmaddadp,701,111100 ..... ..... ..... 01100 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Multiply-Add Type-A Double-Precision,,,,, +109,xvmaddasp,704,111100 ..... ..... ..... 01000 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Multiply-Add Type-A Single-Precision,,,,, +110,xvmaddmsp,704,111100 ..... ..... ..... 01001 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Multiply-Add Type-M Single-Precision,,,,, +111,xvmsubadp,715,111100 ..... ..... ..... 01110 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Multiply-Subtract Type-A Double-Precision,,,,, +112,xvmsubasp,718,111100 ..... ..... ..... 01010 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Multiply-Subtract Type-A Single-Precision,,,,, +113,xvmsubmdp,715,111100 ..... ..... ..... 01111 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Multiply-Subtract Type-M Double-Precision,,,,, +114,xvnmaddadp,727,111100 ..... ..... ..... 11100 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Negative Multiply-Add Type-A Double-Precision,,,,, +115,xvnmaddasp,732,111100 ..... ..... ..... 11000 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Negative Multiply-Add Type-A Single-Precision,,,,, +116,xvnmaddmdp,727,111100 ..... ..... ..... 11101 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Negative Multiply-Add Type-M Double-Precision,,,,, +117,xvnmaddmsp,732,111100 ..... ..... ..... 11001 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Negative Multiply-Add Type-M Single-Precision,,,,, +118,xvnmsubadp,735,111100 ..... ..... ..... 11110 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Negative Multiply-Subtract Type-A Double-Precision,,,,, +119,xvnmsubasp,738,111100 ..... ..... ..... 11010 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Negative Multiply-Subtract Type-A Single-Precision,,,,, +120,xvnmsubmdp,735,111100 ..... ..... ..... 11111 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Negative Multiply-Subtract Type-M Double-Precision,,,,, +121,xvnmsubmsp,738,111100 ..... ..... ..... 11011 001...,XX3_5,XX3,VSR,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Negative Multiply-Subtract Type-M Single-Precision,,,,, +122,stqcx.,872,011111 ..... ..... ..... 00101 101101,X69,X,GPR,GPR,GPR,GPR,XER,CR,,,,,,,I,v2.07,,,Store Quadword Conditional Indexed & record,X,,,, +123,slbieg,1025,011111 ..... ///// ..... 01110 10010/,X3,X,PIDR,LPIDR,GPR,GPR,MSR,SLBE,,,,,,,III,v3.0,P,,SLB Invalidate Entry Global,X,,,, +124,tlbie,1034,011111 ..... /.... ..... 01001 10010/,X57,X,,LPIDR,GPR,GPR,MSR,TLB,,,,,,,III,P1,HV,64,TLB Invalidate Entry,X,,Y,, +125,xsmaddqp[o],576,111111 ..... ..... ..... 01100 00100.,X94,X,VSR,VSR,VSR,FPSCR,MSR,FPSCR,FPSCR,,,,,,I,v3.0,,,VSX Scalar Multiply-Add Quad-Precision [with round to Odd],,,,, +126,xsmsubqp[o],597,111111 ..... ..... ..... 01101 00100.,X94,X,VSR,VSR,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Multiply-Subtract Quad-Precision [with round to Odd],,,,, +127,xsnmaddqp[o],616,111111 ..... ..... ..... 01110 00100.,X94,X,VSR,VSR,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Negative Multiply-Add Quad-Precision [with round to Odd],,,,, +128,xsnmsubqp[o],625,111111 ..... ..... ..... 01111 00100.,X94,X,VSR,VSR,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Negative Multiply-Subtract Quad-Precision [with round to Odd],,,,, +129,stxsdx,498,011111 ..... ..... ..... 10110 01100.,X81,X,,VSR,GPR,GPR,MSR,,,,,,,,I,v2.06,,,Store VSX Scalar Doubleword Indexed,,,,, +130,stxsibx,499,011111 ..... ..... ..... 11100 01101.,X81,X,,VSR,GPR,GPR,MSR,,,,,,,,I,v3.0,,,Store VSX Scalar as Integer Byte Indexed,,,,, +131,stxsihx,499,011111 ..... ..... ..... 11101 01101.,X81,X,,VSR,GPR,GPR,MSR,,,,,,,,I,v3.0,,,Store VSX Scalar as Integer Halfword Indexed,,,,, +132,stxsiwx,500,011111 ..... ..... ..... 00100 01100.,X81,X,,VSR,GPR,GPR,MSR,,,,,,,,I,v2.07,,,Store VSX Scalar as Integer Word Indexed,,,,, +133,stxsspx,502,011111 ..... ..... ..... 10100 01100.,X81,X,,VSR,GPR,GPR,MSR,,,,,,,,I,v2.07,,,Store VSX Scalar Single-Precision Indexed,,,,, +134,stxvb16x,503,011111 ..... ..... ..... 11111 01100.,X81,X,,VSR,GPR,GPR,MSR,,,,,,,,I,v3.0,,,Store VSX Vector Byte*16 Indexed,,,,, +135,stxvd2x,504,011111 ..... ..... ..... 11110 01100.,X81,X,,VSR,GPR,GPR,MSR,,,,,,,,I,v2.06,,,Store VSX Vector Doubleword*2 Indexed,,,,, +136,stxvh8x,505,011111 ..... ..... ..... 11101 01100.,X81,X,,VSR,GPR,GPR,MSR,,,,,,,,I,v3.0,,,Store VSX Vector Halfword*8 Indexed,,,,, +137,stxvl,507,011111 ..... ..... ..... 01100 01101.,X81,X,,VSR,GPR,GPR,MSR,,,,,,,,I,v3.0,,,Store VSX Vector with Length,,,,, +138,stxvll,509,011111 ..... ..... ..... 01101 01101.,X81,X,,VSR,GPR,GPR,MSR,,,,,,,,I,v3.0,,,Store VSX Vector Left-justified with Length,X,,,, +139,stxvw4x,506,011111 ..... ..... ..... 11100 01100.,X81,X,,VSR,GPR,GPR,MSR,,,,,,,,I,v2.06,,,Store VSX Vector Word*4 Indexed,X,,,, +140,stxvx,510,011111 ..... ..... ..... 01100 01100.,X81,X,,VSR,GPR,GPR,MSR,,,,,,,,I,v3.0,,,Store VSX Vector Indexed,,,,, +141,vaddecuq,273,000100 ..... ..... ..... ..... 111101,VA3,VA,VR,VR,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Add Extended & write Carry Unsigned Quadword,,,,, +142,vaddeuqm,273,000100 ..... ..... ..... ..... 111100,VA3,VA,VR,VR,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Add Extended Unsigned Quadword Modulo,,,,, +143,vperm,260,000100 ..... ..... ..... ..... 101011,VA3,VA,VR,VR,VR,,MSR,VR,,,,,,,I,v2.03,,,Vector Permute,,,,, +144,vpermr,260,000100 ..... ..... ..... ..... 111011,VA3,VA,VR,VR,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Permute Right-indexed,,,,, +145,vsel,261,000100 ..... ..... ..... ..... 101010,VA3,VA,VR,VR,VR,,MSR,VR,,,,,,,I,v2.03,,,Vector Select,,,,, +146,vsubecuq,279,000100 ..... ..... ..... ..... 111111,VA3,VA,VR,VR,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Subtract Extended & write Carry Unsigned Quadword,,,,, +147,vsubeuqm,279,000100 ..... ..... ..... ..... 111110,VA3,VA,VR,VR,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Subtract Extended Unsigned Quadword Modulo,,,,, +148,xxperm,772,111100 ..... ..... ..... 00011 010...,XX3_5,XX3,VSR,VSR,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Permute,,,,, +149,xxpermr,772,111100 ..... ..... ..... 00111 010...,XX3_5,XX3,VSR,VSR,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Permute Right-indexed,,,,, +150,xxsel,773,111100 ..... ..... ..... ..... 11....,XX4_1,XX4,VSR,VSR,VSR,,MSR,VSR,,,,,,,I,v2.06,,,VSX Vector Select,,,,, +151,stbcx.,866,011111 ..... ..... ..... 10101 101101,X67,X,,GPR,GPR,GPR,XER,CR,,,,,,,II,v2.06,,,Store Byte Conditional Indexed & record,X,,Y,, +152,stdcx.,869,011111 ..... ..... ..... 00110 101101,X67,X,,GPR,GPR,GPR,XER,CR,,,,,,,II,PPC,,,Store Doubleword Conditional Indexed & record,X,,Y,, +153,sthcx.,867,011111 ..... ..... ..... 10110 101101,X67,X,,GPR,GPR,GPR,XER,CR,,,,,,,II,v2.06,,,Store Halfword Conditional Indexed & record,X,,Y,, +154,stswx,65,011111 ..... ..... ..... 10100 10101/,X66,X,,,GPR,GPR,XER,,,,,,,,I,P1,,,Store String Word Indexed,,,,, +155,stwcx.,868,011111 ..... ..... ..... 00100 101101,X67,X,,GPR,GPR,GPR,XER,CR,,,,,,,II,PPC,,,Store Word Conditional Indexed & record,X,,Y,, +156,add[o][.],69,011111 ..... ..... ..... .1000 01010.,XO4,XO,,,GPR,GPR,,GPR,CR0,XER,,,,,I,P1,,SR,Add,,,Y,,Y +157,addc[o][.],70,011111 ..... ..... ..... .0000 01010.,XO4,XO,,,GPR,GPR,,GPR,XER,XER,,,,,I,P1,,SR,Add Carrying,,,Y,,Y +158,adde[o][.],71,011111 ..... ..... ..... .0100 01010.,XO4,XO,,,GPR,GPR,XER,GPR,XER,XER,,,,,I,P1,,SR,Add Extended,,,Y,,Y +159,addex,72,011111 ..... ..... ..... ..101 01010/,Z23_10,X,,,GPR,GPR,XER,GPR,XER,,,,,,I,v3.0B,,,Add Extended using alternate carry,,,,, +160,addg6s,111,011111 ..... ..... ..... /0010 01010/,XO2,XO,,,GPR,GPR,,GPR,,,,,,,I,v2.06,,,Add & Generate Sixes,,,,, +161,addi,67,001110 ..... ..... ..... ..... ......,D8,D,,,,GPR,,GPR,,,,,,,I,P1,,,Add Immediate,,,Y,,Y +162,addic,69,001100 ..... ..... ..... ..... ......,D8,D,,,,GPR,,GPR,XER,,,,,,I,P1,,SR,Add Immediate Carrying,,,Y,,Y +163,addic.,69,001101 ..... ..... ..... ..... ......,D8,D,,,,GPR,,GPR,CR0,XER,,,,,I,P1,,SR,Add Immediate Carrying & record,,,Y,,Y +164,addis,67,001111 ..... ..... ..... ..... ......,D8,D,,,,GPR,,GPR,,,,,,,I,P1,,,Add Immediate Shifted,,,Y,,Y +165,addme[o][.],71,011111 ..... ..... ///// .0111 01010.,XO1,XO,,,,GPR,XER,GPR,XER,CR0,,,,,I,P1,,SR,Add to Minus One Extended,,,Y,, +166,addpcis,68,010011 ..... ..... ..... ..... 00010.,DX1,DX,,,,,NIA,GPR,,,,,,,I,v3.0,,,Add PC Immediate Shifted,,,Y,, +167,addze[o][.],72,011111 ..... ..... ///// .0110 01010.,XO1,XO,,,,GPR,XER,GPR,XER,CR0,,,,,I,P1,,SR,Add to Zero Extended,,,Y,,Y +168,and[.],94,011111 ..... ..... ..... 00000 11100.,X68,X,,,GPR,GPR,,GPR,CR0,,,,,,I,P1,,SR,AND,,,Y,,Y +169,andc[.],95,011111 ..... ..... ..... 00001 11100.,X68,X,,,GPR,GPR,,GPR,CR0,,,,,,I,P1,,SR,AND with Complement,,,Y,,Y +170,andi.,92,011100 ..... ..... ..... ..... ......,D6,D,,,,GPR,,GPR,CR0,,,,,,I,P1,,SR,AND Immediate & record,,,Y,,Y +171,andis.,92,011101 ..... ..... ..... ..... ......,D6,D,,,,GPR,,GPR,CR0,,,,,,I,P1,,SR,AND Immediate Shifted & record,,,Y,, +172,b[l][a],37,010010 ..... ..... ..... ..... ......,I1,I,,,,,,NIA,LR,,,,,,I,P1,,,Branch [& Link] [Absolute],,,Y,,Y +173,bc[l][a],37,010000 ..... ..... ..... ..... ......,I1,B,,,CR,,,NIA,LR,SPR,,,,,I,P1,,CT,Branch Conditional [& Link] [Absolute],,,Y,,Y +174,bcctr[l],38,010011 ..... ..... ///.. 10000 10000.,XL4,XL,,,CR,,SPR,NIA,LR,,,,,,I,P1,,CT,Branch Conditional to CTR [& Link],,,Y,,Y +175,bcdadd.,348,000100 ..... ..... ..... 1.000 000001,VX16,VX,,VR,VR,,MSR,VR,CR,,,,,,I,v2.07,,,Decimal Add Modulo & record,,,,, +176,bcdcfn.,350,000100 ..... 00111 ..... 1.110 000001,VX9,VX,,,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Decimal Convert From National & record,,,,, +177,bcdcfsq.,354,000100 ..... 00010 ..... 1.110 000001,VX9,VX,,,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Decimal Convert From Signed Quadword & record,,,,, +178,bcdcfz.,351,000100 ..... 00110 ..... 1.110 000001,VX9,VX,,,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Decimal Convert From Zoned & record,,,,, +179,bcdcpsgn.,356,000100 ..... ..... ..... 01101 000001,VX17,VX,,VR,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Decimal CopySign & record,,,,, +180,bcdctn.,352,000100 ..... 00101 ..... 1/110 000001,VX8,VX,,,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Decimal Convert To National & record,,,,, +181,bcdctsq.,354,000100 ..... 00000 ..... 1/110 000001,VX8,VX,,,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Decimal Convert To Signed Quadword & record,,,,, +182,bcdctz.,353,000100 ..... 00100 ..... 1.110 000001,VX9,VX,,,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Decimal Convert To Zoned & record,,,,, +183,bcds.,357,000100 ..... ..... ..... 1.011 000001,VX16,VX,,VR,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Decimal Shift & record,,,,, +184,bcdsetsgn.,356,000100 ..... 11111 ..... 1.110 000001,VX9,VX,,,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Decimal Set Sign & record,,,,, +185,bcdsr.,359,000100 ..... ..... ..... 1.111 000001,VX16,VX,,VR,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Decimal Shift & Round & record,,,,, +186,bcdsub.,348,000100 ..... ..... ..... 1.001 000001,VX16,VX,,VR,VR,,MSR,VR,CR,,,,,,I,v2.07,,,Decimal Subtract Modulo & record,,,,, +187,bcdtrunc.,360,000100 ..... ..... ..... 1.100 000001,VX16,VX,,VR,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Decimal Truncate & record,,,,, +188,bcdus.,358,000100 ..... ..... ..... 1/010 000001,VX15,VX,,VR,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Decimal Unsigned Shift & record,,,,, +189,bcdutrunc.,361,000100 ..... ..... ..... 1/101 000001,VX15,VX,,VR,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Decimal Unsigned Truncate & record,,,,, +190,bclr[l],38,010011 ..... ..... ///.. 00000 10000.,XL4,XL,,,CR,,LR,NIA,LR,SPR,,,,,I,P1,,CT,Branch Conditional to LR [& Link],,,Y,,Y +191,bctar[l],39,010011 ..... ..... ///.. 10001 10000.,XL4,XL,,,CR,,SPR,NIA,LR,SPR,,,,,I,v2.07,,,Branch Conditional to BTAR [& Link],,,Y,,Y +192,bpermd,100,011111 ..... ..... ..... 00111 11100/,X66,X,,,GPR,GPR,,GPR,,,,,,,I,v2.06,,,Bit Permute Doubleword,,,,, +193,cbcdtd,111,011111 ..... ..... ///// 01001 11010/,X60,X,,,,GPR,,GPR,,,,,,,I,v2.06,,,Convert Binary Coded Decimal To Declets,,,,, +194,cdtbcd,111,011111 ..... ..... ///// 01000 11010/,X60,X,,,,GPR,,GPR,,,,,,,I,v2.06,,,Convert Declets To Binary Coded Decimal,,,,, +195,clrbhrb,909,011111 ///// ///// ///// 01101 01110/,X1,X,,,,,,BHRB,,,,,,,I,v2.07,,,Clear BHRB,,,,, +196,cmp,85,011111 .../. ..... ..... 00000 00000/,X30,X,,,GPR,GPR,XER,CR,,,,,,,I,P1,,,Compare,,,Y,Y,Y +197,cmpb,97,011111 ..... ..... ..... 01111 11100/,X66,X,,,GPR,GPR,,GPR,,,,,,,I,v2.05,,,Compare Byte,,,Y,, +198,cmpeqb,88,011111 ...// ..... ..... 00111 00000/,X25,X,,,GPR,GPR,,CR,,,,,,,I,v3.0,,,Compare Equal Byte,,,,, +199,cmpi,85,001011 .../. ..... ..... ..... ......,D1,D,,,,GPR,XER,CR,,,,,,,I,P1,,,Compare Immediate,,,Y,,Y +200,cmpl,86,011111 .../. ..... ..... 00001 00000/,X30,X,,,GPR,GPR,XER,CR,,,,,,,I,P1,,,Compare Logical,,,Y,Y,Y +201,cmpli,86,001010 .../. ..... ..... ..... ......,D2,D,,,,GPR,XER,CR,,,,,,,I,P1,,,Compare Logical Immediate,,,Y,,Y +202,cmprb,87,011111 .../. ..... ..... 00110 00000/,X30,X,,,GPR,GPR,,CR,,,,,,,I,v3.0,,,Compare Ranged Byte,,,,, +203,cntlzd[.],99,011111 ..... ..... ///// 00001 11010.,X62,X,,,,GPR,,GPR,CR0,,,,,,I,PPC,,SR,Count Leading Zeros Doubleword,,,Y,,Y +204,cntlzw[.],96,011111 ..... ..... ///// 00000 11010.,X62,X,,,,GPR,,GPR,CR0,,,,,,I,P1,,SR,Count Leading Zeros Word,,,Y,,Y +205,cnttzd[.],99,011111 ..... ..... ///// 10001 11010.,X62,X,,,,GPR,,GPR,CR0,,,,,,I,v3.0,,,Count Trailing Zeros Doubleword,,,Y,, +206,cnttzw[.],96,011111 ..... ..... ///// 10000 11010.,X62,X,,,,GPR,,GPR,CR0,,,,,,I,v3.0,,,Count Trailing Zeros Word,,,Y,, +207,copy,855,011111 ////. ..... ..... 11000 00110/,X6,X,,,GPR,GPR,,,,,,,,,II,v3.0,,,Copy,,,,, +208,cpabort,856,011111 ///// ///// ///// 11010 00110/,X1,X,,,,,,,,,,,,,II,v3.0,,,CP_Abort,,,,, +209,crand,40,010011 ..... ..... ..... 01000 00001/,XL5,XL,,,CR,,,CR,,,,,,,I,P1,,,CR AND,,,Y,Y, +210,crandc,41,010011 ..... ..... ..... 00100 00001/,XL5,XL,,,CR,,,CR,,,,,,,I,P1,,,CR AND with Complement,,,Y,Y, +211,creqv,41,010011 ..... ..... ..... 01001 00001/,XL5,XL,,,CR,,,CR,,,,,,,I,P1,,,CR Equivalent,,,Y,Y, +212,crnand,40,010011 ..... ..... ..... 00111 00001/,XL5,XL,,,CR,,,CR,,,,,,,I,P1,,,CR NAND,,,Y,Y, +213,crnor,41,010011 ..... ..... ..... 00001 00001/,XL5,XL,,,CR,,,CR,,,,,,,I,P1,,,CR NOR,,,Y,Y, +214,cror,40,010011 ..... ..... ..... 01110 00001/,XL5,XL,,,CR,,,CR,,,,,,,I,P1,,,CR OR,,,Y,Y, +215,crorc,41,010011 ..... ..... ..... 01101 00001/,XL5,XL,,,CR,,,CR,,,,,,,I,P1,,,CR OR with Complement,,,Y,Y, +216,crxor,40,010011 ..... ..... ..... 00110 00001/,XL5,XL,,,CR,,,CR,,,,,,,I,P1,,,CR XOR,,,Y,Y, +217,darn,78,011111 ..... ///.. ///// 10111 10011/,X73,X,,,,,,GPR,,,,,,,I,v3.0,,,Deliver A Random Number,,,,, +218,dcbf,852,011111 ///.. ..... ..... 00010 10110/,X10,X,,,GPR,GPR,,,,,,,,,II,PPC,,,Data Cache Block Flush,,,Y,, +219,dcbst,851,011111 ///// ..... ..... 00001 10110/,X6,X,,,GPR,GPR,,,,,,,,,II,PPC,,,Data Cache Block Store,,X,Y,, +220,dcbt,849,011111 ..... ..... ..... 01000 10110/,X85,X,,,GPR,GPR,,,,,,,,,II,PPC,,,Data Cache Block Touch,,X,Y,, +221,dcbtst,850,011111 ..... ..... ..... 00111 10110/,X85,X,,,GPR,GPR,,,,,,,,,II,PPC,,,Data Cache Block Touch for Store,,X,Y,, +222,dcbz,851,011111 ///// ..... ..... 11111 10110/,X6,X,,,GPR,GPR,,,,,,,,,II,P1,,,Data Cache Block Zero,,X,Y,, +223,dcmpo,199,111011 ...// ..... ..... 00100 00010/,X22,X,,,FPR,FPR,,CR,FPSCR,,,,,,I,v2.05,,,DFP Compare Ordered,,,,, +224,dcmpu,198,111011 ...// ..... ..... 10100 00010/,X22,X,,,FPR,FPR,,CR,FPSCR,FPSCR,,,,,I,v2.05,,,DFP Compare Unordered,,,,, +225,ddedpd[.],217,111011 ..... ../// ..... 01010 00010.,X47,X,,,,FPR,,FPR,CR1,,,,,,I,v2.05,,,DFP Decode DPD To BCD,,,,, +226,ddedpdq[.],217,111111 ..... ../// ..... 01010 00010.,X54,X,,,FPR,FPR,,FPR,FPR,CR1,,,,,I,v2.05,,,DFP Decode DPD To BCD Quad,,,,, +227,diex[.],218,111011 ..... ..... ..... 11011 00010.,X44,X,,,,,,,,,,,,,I,v2.05,,,DFP Insert Exponent,,,,, +228,diexq[.],218,111111 ..... ..... ..... 11011 00010.,X50,X,,FPR,FPR,FPR,,FPR,FPR,CR1,,,,,I,v2.05,,,DFP Insert Exponent Quad,,,,, +229,divd[o][.],81,011111 ..... ..... ..... .1111 01001.,XO4,XO,,,GPR,GPR,,GPR,CR0,XER,,,,,I,PPC,,SR,Divide Doubleword,,X,Y,,Y +230,divde[o][.],82,011111 ..... ..... ..... .1101 01001.,XO4,XO,,,GPR,GPR,,GPR,CR0,XER,,,,,I,v2.06,,SR,Divide Doubleword Extended,,X,Y,,Y +231,divdeu[o][.],82,011111 ..... ..... ..... .1100 01001.,XO4,XO,,,GPR,GPR,,GPR,CR0,XER,,,,,I,v2.06,,SR,Divide Doubleword Extended Unsigned,,X,Y,, +232,divdu[o][.],81,011111 ..... ..... ..... .1110 01001.,XO4,XO,,,GPR,GPR,,GPR,CR0,XER,,,,,I,PPC,,SR,Divide Doubleword Unsigned,,X,Y,, +233,divw[o][.],74,011111 ..... ..... ..... .1111 01011.,XO4,XO,,,GPR,GPR,,GPR,CR0,XER,,,,,I,PPC,,SR,Divide Word,,X,Y,, +234,divwe[o][.],75,011111 ..... ..... ..... .1101 01011.,XO4,XO,,,GPR,GPR,,GPR,CR0,XER,,,,,I,v2.06,,SR,Divide Word Extended,,X,Y,, +235,divweu[o][.],75,011111 ..... ..... ..... .1100 01011.,XO4,XO,,,GPR,GPR,,GPR,CR0,XER,,,,,I,v2.06,,SR,Divide Word Extended Unsigned,,X,Y,, +236,divwu[o][.],74,011111 ..... ..... ..... .1110 01011.,XO4,XO,,,GPR,GPR,,GPR,CR0,XER,,,,,I,PPC,,SR,Divide Word Unsigned,,X,Y,,Y +237,dscli[.],220,111011 ..... ..... ..... .0010 00010.,Z22_5,Z22,,,,FPR,,FPR,CR1,,,,,,I,v2.05,,,DFP Shift Significand Left Immediate,,,,, +238,dscliq[.],220,111111 ..... ..... ..... .0010 00010.,Z22_6,Z22,,,FPR,FPR,,FPR,FPR,CR1,,,,,I,v2.05,,,DFP Shift Significand Left Immediate Quad,,,,, +239,dscri[.],220,111011 ..... ..... ..... .0011 00010.,Z22_5,Z22,,,,FPR,,FPR,CR1,,,,,,I,v2.05,,,DFP Shift Significand Right Immediate,,,,, +240,dscriq[.],220,111111 ..... ..... ..... .0011 00010.,Z22_6,Z22,,,FPR,FPR,,FPR,FPR,CR1,,,,,I,v2.05,,,DFP Shift Significand Right Immediate Quad,,,,, +241,dtstdc,200,111011 ...// ..... ..... .0110 00010/,Z22_1,Z22,,,,FPR,,CR,FPSCR,,,,,,I,v2.05,,,DFP Test Data Class,,,,, +242,dtstdcq,200,111111 ...// ..... ..... .0110 00010/,Z22_3,Z22,,,FPR,FPR,,CR,FPSCR,,,,,,I,v2.05,,,DFP Test Data Class Quad,,,,, +243,dtstdg,200,111011 ...// ..... ..... .0111 00010/,Z22_2,Z22,,,,FPR,,CR,FPSCR,,,,,,I,v2.05,,,DFP Test Data Group,,,,, +244,dtstdgq,200,111111 ...// ..... ..... .0111 00010/,Z22_4,Z22,,,FPR,FPR,,CR,FPSCR,,,,,,I,v2.05,,,DFP Test Data Group Quad,,,,, +245,dtstex,201,111011 ...// ..... ..... 00101 00010/,X22,X,,,FPR,FPR,,CR,FPSCR,,,,,,I,v2.05,,,DFP Test Exponent,,,,, +246,dtstsf,202,111011 ...// ..... ..... 10101 00010/,X22,X,,,FPR,FPR,,CR,FPSCR,,,,,,I,v2.05,,,DFP Test Significance,,,,, +247,dtstsfi,202,111011 ...// ..... ..... 10101 00011/,X26,X,,,,FPR,,CR,FPSCR,,,,,,I,v3.0,,,DFP Test Significance Immediate,,,,, +248,dtstsfiq,202,111111 ...// ..... ..... 10101 00011/,X27,X,,,FPR,FPR,,CR,FPSCR,,,,,,I,v3.0,,,DFP Test Significance Immediate Quad,,,,, +249,dtstsfq,202,111111 ...// ..... ..... 10101 00010/,X23,X,,FPR,FPR,FPR,,CR,FPSCR,,,,,,I,v2.05,,,DFP Test Significance Quad,,,,, +250,dxex[.],218,111011 ..... ///// ..... 01011 00010.,X36,X,,,,FPR,,FPR,CR1,,,,,,I,v2.05,,,DFP Extract Exponent,,,,, +251,dxexq[.],218,111111 ..... ///// ..... 01011 00010.,X37,X,,,FPR,FPR,,FPR,CR1,,,,,,I,v2.05,,,DFP Extract Exponent Quad,,,,, +252,eieio,875,011111 ///// ///// ///// 11010 10110/,X1,X,,,,,,,,,,,,,II,PPC,,,Enforce In-order Execution of I/O,,,Y,, +253,eqv[.],95,011111 ..... ..... ..... 01000 11100.,X68,X,,,GPR,GPR,,GPR,CR0,,,,,,I,P1,,SR,Equivalent,,,Y,, +254,extsb[.],96,011111 ..... ..... ///// 11101 11010.,X62,X,,,,GPR,,GPR,CR0,,,,,,I,PPC,,SR,Extend Sign Byte,,,Y,,Y +255,extsh[.],96,011111 ..... ..... ///// 11100 11010.,X62,X,,,,GPR,,GPR,CR0,,,,,,I,P1,,SR,Extend Sign Halfword,,,Y,, +256,extsw[.],99,011111 ..... ..... ///// 11110 11010.,X62,X,,,,GPR,,GPR,CR0,,,,,,I,PPC,,SR,Extend Sign Word,,,Y,,Y +257,extswsli[.],110,011111 ..... ..... ..... 11011 1101..,XS1,XS,,,,GPR,,GPR,CR0,,,,,,I,v3.0,,,Extend Sign Word & Shift Left Immediate,,,Y,, +258,fabs[.],150,111111 ..... ///// ..... 01000 01000.,X36,X,,,,FPR,,FPR,CR1,,,,,,I,P1,,,Floating Absolute,,,,, +259,fcmpo,167,111111 ...// ..... ..... 00001 00000/,X22,X,,,FPR,FPR,,CR,FPSCR,,,,,,I,P1,,,Floating Compare Ordered,,,,, +260,fcmpu,167,111111 ...// ..... ..... 00000 00000/,X22,X,,,FPR,FPR,,CR,FPSCR,,,,,,I,P1,,,Floating Compare Unordered,,,,, +261,fcpsgn[.],150,111111 ..... ..... ..... 00000 01000.,X44,X,,,FPR,FPR,,FPR,CR1,,,,,,I,v2.05,,,Floating Copy Sign,,,,, +262,fmr[.],150,111111 ..... ///// ..... 00010 01000.,X36,X,,,,FPR,,FPR,CR1,,,,,,I,P1,,,Floating Move Register,,,,, +263,fmrgew,151,111111 ..... ..... ..... 11110 00110/,X43,X,,,FPR,FPR,MSR,FPR,,,,,,,I,v2.07,,,Floating Merge Even Word,,,,, +264,fmrgow,151,111111 ..... ..... ..... 11010 00110/,X43,X,,,FPR,FPR,MSR,FPR,,,,,,,I,v2.07,,,Floating Merge Odd Word,,,,, +265,fmuls[.],153,111011 ..... ..... ///// ..... 11001.,A2,A,,,,,,,,,,,,,I,PPC,,,Floating Multiply Single,,,,, +266,fnabs[.],150,111111 ..... ///// ..... 00100 01000.,X36,X,,,,FPR,,FPR,CR1,,,,,,I,P1,,,Floating Negative Absolute Value,,,,, +267,fneg[.],150,111111 ..... ///// ..... 00001 01000.,X36,X,,,,FPR,,FPR,CR1,,,,,,I,P1,,,Floating Negate,,,,, +268,fsel[.],168,111111 ..... ..... ..... ..... 10111.,A4,A,,FPR,FPR,FPR,,FPR,CR1,,,,,,I,PPC,,,Floating Select,,,,, +269,ftdiv,156,111111 ...// ..... ..... 00100 00000/,X22,X,,,FPR,FPR,,CR,,,,,,,I,v2.06,,,Floating Test for software Divide,,X,,, +270,ftsqrt,156,111111 ...// ///// ..... 00101 00000/,X19,X,,,,FPR,,CR,,,,,,,I,v2.06,,,Floating Test for software Square Root,,,,, +271,hrfid,956,010011 ///// ///// ///// 01000 10010/,XL1,XL,,,,SPR,MSR,MSR,NIA,,,,,,III,v2.02,HV,,Return From Interrupt Doubleword Hypervisor,,,,, +272,icbi,840,011111 ///// ..... ..... 11110 10110/,X6,X,,,GPR,GPR,,,,,,,,,II,PPC,,,Instruction Cache Block Invalidate,,X,,, +273,icbt,840,011111 /.... ..... ..... 00000 10110/,X15,X,,,GPR,GPR,,,,,,,,,II,v2.07,,,Instruction Cache Block Touch,,X,,, +274,isel,91,011111 ..... ..... ..... ..... 01111/,A5,A,,CR,GPR,GPR,,GPR,,,,,,,I,v2.03,,,Integer Select,,,,Y, +275,isync,863,010011 ///// ///// ///// 00100 10110/,XL1,XL,,,,,,,,,,,,Y,II,P1,,,Instruction Synchronize,,,Y,, +276,lbarx,864,011111 ..... ..... ..... 00001 10100.,X78,X,,,GPR,GPR,,GPR,,,,,,,II,v2.06,,,Load Byte And Reserve Indexed,X,,Y,, +277,lbz,48,100010 ..... ..... ..... ..... ......,D7,D,,,,GPR,,GPR,,,,,,,I,P1,,,Load Byte & Zero,,,Y,,Y +278,lbzcix,966,011111 ..... ..... ..... 11010 10101/,X77,X,,,GPR,GPR,,GPR,,,,,,,III,v2.05,HV,,Load Byte & Zero Caching Inhibited Indexed,X,,Y,, +279,lbzu,48,100011 ..... ..... ..... ..... ......,D7,D,,,,GPR,,GPR,GPR,,,,,,I,P1,,,Load Byte & Zero with Update,,,Y,,Y +280,lbzux,48,011111 ..... ..... ..... 00011 10111/,X77,X,,,GPR,GPR,,GPR,GPR,,,,,,I,P1,,,Load Byte & Zero with Update Indexed,,,Y,, +281,lbzx,48,011111 ..... ..... ..... 00010 10111/,X77,X,,,GPR,GPR,,GPR,,,,,,,I,P1,,,Load Byte & Zero Indexed,,,Y,,Y +282,ld,53,111010 ..... ..... ..... ..... ....00,DS5,DS,,,,GPR,,GPR,,,,,,,I,PPC,,,Load Doubleword,,,Y,,Y +283,ldarx,869,011111 ..... ..... ..... 00010 10100/,X78,X,,,GPR,GPR,,GPR,,,,,,,II,PPC,,,Load Doubleword And Reserve Indexed,X,,Y,, +284,ldat,860,011111 ..... ..... ..... 10011 00110/,X75,X,,,,GPR,,GPR,,,,,"function code field determines behavior, including source registers",,II,v3.0,,,Load Doubleword ATomic,X,,,, +285,ldbrx,61,011111 ..... ..... ..... 10000 10100/,X77,X,,,,GPR,,GPR,,,,,,,I,v2.06,,,Load Doubleword Byte-Reverse Indexed,X,,Y,, +286,ldcix,966,011111 ..... ..... ..... 11011 10101/,X77,X,,,GPR,GPR,,GPR,,,,,,,III,v2.05,HV,,Load Doubleword Caching Inhibited Indexed,X,,Y,, +287,ldu,53,111010 ..... ..... ..... ..... ....01,DS5,DS,,,,GPR,,GPR,GPR,,,,,,I,PPC,,,Load Doubleword with Update,,,Y,,Y +288,ldux,53,011111 ..... ..... ..... 00001 10101/,X77,X,,,GPR,GPR,,GPR,GPR,,,,,,I,PPC,,,Load Doubleword with Update Indexed,,,Y,, +289,ldx,53,011111 ..... ..... ..... 00000 10101/,X77,X,,,GPR,GPR,,GPR,,,,,,,I,PPC,,,Load Doubleword Indexed,,,Y,,Y +290,lfd,142,110010 ..... ..... ..... ..... ......,D4,D,,,,GPR,,FPR,,,,,,,I,P1,,,Load Floating Double,,,,, +291,lfdp,149,111001 ..... ..... ..... ..... ....00,DS2,DS,,,,GPR,,FPR,FPR,,,,,,I,v2.05,,,Load Floating Double Pair,,,,, +292,lfdpx,149,011111 ..... ..... ..... 11000 10111/,X52,X,,,GPR,GPR,,FPR,FPR,,,,,,I,v2.05,,,Load Floating Double Pair Indexed,,,,, +293,lfdu,142,110011 ..... ..... ..... ..... ......,D4,D,,,,GPR,,FPR,GPR,,,,,,I,P1,,,Load Floating Double with Update,,,,, +294,lfdux,143,011111 ..... ..... ..... 10011 10111/,X45,X,,,GPR,GPR,,FPR,GPR,,,,,,I,P1,,,Load Floating Double with Update Indexed,,,,, +295,lfdx,142,011111 ..... ..... ..... 10010 10111/,X45,X,,,GPR,GPR,,FPR,,,,,,,I,P1,,,Load Floating Double Indexed,,,,, +296,lfiwax,143,011111 ..... ..... ..... 11010 10111/,X45,X,,,GPR,GPR,,FPR,,,,,,,I,v2.05,,,Load Floating as Integer Word Algebraic Indexed,,,,, +297,lfiwzx,143,011111 ..... ..... ..... 11011 10111/,X45,X,,,GPR,GPR,,FPR,,,,,,,I,v2.06,,,Load Floating as Integer Word & Zero Indexed,,,,, +298,lfs,140,110000 ..... ..... ..... ..... ......,D4,D,,,,GPR,,FPR,,,,,,,I,P1,,,Load Floating Single,,,,, +299,lfsu,141,110001 ..... ..... ..... ..... ......,D4,D,,,,GPR,,FPR,GPR,,,,,,I,P1,,,Load Floating Single with Update,,,,, +300,lfsux,142,011111 ..... ..... ..... 10001 10111/,X45,X,,,GPR,GPR,,FPR,GPR,,,,,,I,P1,,,Load Floating Single with Update Indexed,,,,, +301,lfsx,141,011111 ..... ..... ..... 10000 10111/,X45,X,,,GPR,GPR,,FPR,,,,,,,I,P1,,,Load Floating Single Indexed,,,,, +302,lha,50,101010 ..... ..... ..... ..... ......,D7,D,,,,GPR,,GPR,,,,,,,I,P1,,,Load Halfword Algebraic,,,Y,, +303,lharx,865,011111 ..... ..... ..... 00011 10100.,X78,X,,,GPR,GPR,,GPR,,,,,,,II,v2.06,,,Load Halfword And Reserve Indexed Xform,X,,Y,, +304,lhau,50,101011 ..... ..... ..... ..... ......,D7,D,,,,GPR,,GPR,GPR,,,,,,I,P1,,,Load Halfword Algebraic with Update,,,Y,, +305,lhaux,50,011111 ..... ..... ..... 01011 10111/,X77,X,,,GPR,GPR,,GPR,GPR,,,,,,I,P1,,,Load Halfword Algebraic with Update Indexed,,,Y,, +306,lhax,50,011111 ..... ..... ..... 01010 10111/,X77,X,,,GPR,GPR,,GPR,,,,,,,I,P1,,,Load Halfword Algebraic Indexed,,,Y,,Y +307,lhbrx,60,011111 ..... ..... ..... 11000 10110/,X77,X,,,GPR,GPR,,GPR,,,,,,,I,P1,,,Load Halfword Byte-Reverse Indexed,X,,Y,, +308,lhz,49,101000 ..... ..... ..... ..... ......,D7,D,,,,GPR,,GPR,,,,,,,I,P1,,,Load Halfword & Zero,,,Y,,Y +309,lhzcix,966,011111 ..... ..... ..... 11001 10101/,X77,X,,,GPR,GPR,,GPR,,,,,,,III,v2.05,HV,,Load Halfword & Zero Caching Inhibited Indexed,X,,Y,, +310,lhzu,49,101001 ..... ..... ..... ..... ......,D7,D,,,,GPR,,GPR,GPR,,,,,,I,P1,,,Load Halfword & Zero with Update,,,Y,,Y +311,lhzux,49,011111 ..... ..... ..... 01001 10111/,X77,X,,,GPR,GPR,,GPR,GPR,,,,,,I,P1,,,Load Halfword & Zero with Update Indexed,,,Y,, +312,lhzx,49,011111 ..... ..... ..... 01000 10111/,X77,X,,,GPR,GPR,,GPR,,,,,,,I,P1,,,Load Halfword & Zero Indexed,,,Y,, +313,lmw,62,101110 ..... ..... ..... ..... ......,D7,D,,,,GPR,,GPR*,,,,,GPRs [31-RT:31] are loaded from consecutive addresses in storage,,I,P1,,,Load Multiple Word,X,,,, +314,lq,58,111000 ..... ..... ..... ..... ......,DQ1,DQ,,,,GPR,,GPR,GPR,,,,,,I,v2.03,,,Load Quadword,,,,, +315,lqarx,871,011111 ..... ..... ..... 01000 10100.,X79,X,,,GPR,GPR,,GPR,GPR,,,,,,I,v2.07,,,Load Quadword And Reserve Indexed,,,,, +316,lswi,64,011111 ..... ..... ..... 10010 10101/,X76,X,,,,GPR,,GPR*,,,,,variable number of GPRs are loaded with contents from storage,,I,P1,,,Load String Word Immediate,,,,, +317,lswx,64,011111 ..... ..... ..... 10000 10101/,X77,X,,,GPR,GPR,,GPR*,,,,,variable number of GPRs are loaded with contents from storage,,I,P1,,,Load String Word Indexed,,,,, +318,lvebx,242,011111 ..... ..... ..... 00000 00111/,X92,X,,,GPR,GPR,,VR,,,,,,,I,v2.03,,,Load Vector Element Byte Indexed,,,,, +319,lvehx,242,011111 ..... ..... ..... 00001 00111/,X92,X,,,GPR,GPR,,VR,,,,,,,I,v2.03,,,Load Vector Element Halfword Indexed,,,,, +320,lvewx,243,011111 ..... ..... ..... 00010 00111/,X92,X,,,GPR,GPR,,VR,,,,,,,I,v2.03,,,Load Vector Element Word Indexed,,,,, +321,lvsl,247,011111 ..... ..... ..... 00000 00110/,X92,X,,,GPR,GPR,,VR,,,,,,,I,v2.03,,,Load Vector for Shift Left,,,,, +322,lvsr,247,011111 ..... ..... ..... 00001 00110/,X92,X,,,GPR,GPR,,VR,,,,,,,I,v2.03,,,Load Vector for Shift Right,,,,, +323,lvx,243,011111 ..... ..... ..... 00011 00111/,X92,X,,,GPR,GPR,,VR,,,,,,,I,v2.03,,,Load Vector Indexed,,,,, +324,lvxl,243,011111 ..... ..... ..... 01011 00111/,X92,X,,,GPR,GPR,,VR,,,,,,,I,v2.03,,,Load Vector Indexed Last,,,,, +325,lwa,52,111010 ..... ..... ..... ..... ....10,DS5,DS,,,,GPR,,GPR,,,,,,,I,PPC,,,Load Word Algebraic,,,Y,,Y +326,lwarx,865,011111 ..... ..... ..... 00000 10100/,X78,X,,,GPR,GPR,,GPR,,,,,,,II,PPC,,,Load Word & Reserve Indexed,X,,Y,, +327,lwat,860,011111 ..... ..... ..... 10010 00110/,X75,X,,,,GPR,,GPR,,,,,"function code field determines behavior, including source registers",,II,v3.0,,,Load Word ATomic,X,,,, +328,lwaux,52,011111 ..... ..... ..... 01011 10101/,X77,X,,,GPR,GPR,,GPR,GPR,,,,,,I,PPC,,,Load Word Algebraic with Update Indexed,,,Y,, +329,lwax,52,011111 ..... ..... ..... 01010 10101/,X77,X,,,GPR,GPR,,GPR,,,,,,,I,PPC,,,Load Word Algebraic Indexed,,,Y,,Y +330,lwbrx,60,011111 ..... ..... ..... 10000 10110/,X77,X,,,GPR,GPR,,GPR,,,,,,,I,P1,,,Load Word Byte-Reverse Indexed,X,,Y,, +331,lwz,51,100000 ..... ..... ..... ..... ......,D7,D,,,,GPR,,GPR,,,,,,,I,P1,,,Load Word & Zero,,,Y,,Y +332,lwzcix,966,011111 ..... ..... ..... 11000 10101/,X77,X,,,GPR,GPR,,GPR,,,,,,,III,v2.05,HV,,Load Word & Zero Caching Inhibited Indexed,X,,Y,, +333,lwzu,51,100001 ..... ..... ..... ..... ......,D7,D,,,,GPR,,GPR,GPR,,,,,,I,P1,,,Load Word & Zero with Update,,,Y,, +334,lwzux,51,011111 ..... ..... ..... 00001 10111/,X77,X,,,GPR,GPR,,GPR,GPR,,,,,,I,P1,,,Load Word & Zero with Update Indexed,,,Y,, +335,lwzx,51,011111 ..... ..... ..... 00000 10111/,X77,X,,,GPR,GPR,,GPR,,,,,,,I,P1,,,Load Word & Zero Indexed,,,Y,,Y +336,lxsd,480,111001 ..... ..... ..... ..... ....10,DS7,DS,,,,GPR,MSR,VSR,,,,,,,I,v3.0,,,Load VSX Scalar Doubleword,,,,, +337,lxsdx,480,011111 ..... ..... ..... 10010 01100.,X84,X,,,GPR,GPR,MSR,VSR,,,,,,,I,v2.06,,,Load VSX Scalar Doubleword Indexed,,,,, +338,lxsibzx,482,011111 ..... ..... ..... 11000 01101.,X84,X,,,GPR,GPR,MSR,VSR,,,,,,,I,v3.0,,,Load VSX Scalar as Integer Byte & Zero Indexed,,,,, +339,lxsihzx,482,011111 ..... ..... ..... 11001 01101.,X84,X,,,GPR,GPR,MSR,VSR,,,,,,,I,v3.0,,,Load VSX Scalar as Integer Halfword & Zero Indexed,,,,, +340,lxsiwax,483,011111 ..... ..... ..... 00010 01100.,X84,X,,,GPR,GPR,MSR,VSR,,,,,,,I,v2.07,,,Load VSX Scalar as Integer Word Algebraic Indexed,,,,, +341,lxsiwzx,484,011111 ..... ..... ..... 00000 01100.,X84,X,,,GPR,GPR,MSR,VSR,,,,,,,I,v2.07,,,Load VSX Scalar as Integer Word & Zero Indexed,,,,, +342,lxssp,485,111001 ..... ..... ..... ..... ....11,DS7,DS,,,,GPR,MSR,VSR,,,,,,,I,v3.0,,,Load VSX Scalar Single,,,,, +343,lxsspx,485,011111 ..... ..... ..... 10000 01100.,X84,X,,,GPR,GPR,MSR,VSR,,,,,,,I,v2.07,,,Load VSX Scalar Single-Precision Indexed,,,,, +344,lxv,492,111101 ..... ..... ..... ..... ...001,DQ3,DQ,,,,GPR,MSR,VSR,,,,,,,I,v3.0,,,Load VSX Vector,,,,, +345,lxvb16x,487,011111 ..... ..... ..... 11011 01100.,X84,X,,,GPR,GPR,MSR,VSR,,,,,,,I,v3.0,,,Load VSX Vector Byte*16 Indexed,,,,, +346,lxvd2x,488,011111 ..... ..... ..... 11010 01100.,X84,X,,,GPR,GPR,MSR,VSR,,,,,,,I,v2.06,,,Load VSX Vector Doubleword*2 Indexed,,,,, +347,lxvdsx,494,011111 ..... ..... ..... 01010 01100.,X84,X,,,GPR,GPR,MSR,VSR,,,,,,,I,v2.06,,,Load VSX Vector Doubleword & Splat Indexed,,,,, +348,lxvh8x,495,011111 ..... ..... ..... 11001 01100.,X84,X,,,GPR,GPR,MSR,VSR,,,,,,,I,v3.0,,,Load VSX Vector Halfword*8 Indexed,,,,, +349,lxvl,489,011111 ..... ..... ..... 01000 01101.,X84,X,,,GPR,GPR,MSR,VSR,,,,,,,I,v3.0,,,Load VSX Vector with Length,,,,, +350,lxvll,491,011111 ..... ..... ..... 01001 01101.,X84,X,,,GPR,GPR,MSR,VSR,,,,,,,I,v3.0,,,Load VSX Vector Left-justified with Length,,,,, +351,lxvw4x,496,011111 ..... ..... ..... 11000 01100.,X84,X,,,GPR,GPR,MSR,VSR,,,,,,,I,v2.06,,,Load VSX Vector Word*4 Indexed,,,,, +352,lxvwsx,497,011111 ..... ..... ..... 01011 01100.,X84,X,,,GPR,GPR,MSR,VSR,,,,,,,I,v3.0,,,Load VSX Vector Word & Splat Indexed,,,,, +353,lxvx,492,011111 ..... ..... ..... 01000 01100.,X84,X,,,GPR,GPR,MSR,VSR,,,,,,,I,v3.0,,,Load VSX Vector Indexed,,,,, +354,maddhd,80,000100 ..... ..... ..... ..... 110000,VA1,VA,,GPR,GPR,GPR,,GPR,,,,,,,I,v3.0,,,Multiply-Add High Doubleword,,,,, +355,maddhdu,80,000100 ..... ..... ..... ..... 110001,VA1,VA,,GPR,GPR,GPR,,GPR,,,,,,,I,v3.0,,,Multiply-Add High Doubleword Unsigned,,,,, +356,maddld,80,000100 ..... ..... ..... ..... 110011,VA1,VA,,GPR,GPR,GPR,,GPR,,,,,,,I,v3.0,,,Multiply-Add Low Doubleword,,,,, +357,mcrf,41,010011 ...// ...// ///// 00000 00000/,XL3,XL,,,CR,,,CR,,,,,,,I,P1,,,Move CR Field,,,Y,Y, +358,mcrfs,171,111111 ...// ...// ///// 00010 00000/,X21,X,,,,,FPSCR,CR,FPSCR,,,,,,I,P1,,,Move To CR from FPSCR,,,,, +359,mcrxrx,120,011111 ...// ///// ///// 10010 00000/,X18,X,,,,,XER,CR,,,,,,,I,v3.0,,,Move XER to CR Extended,,,,, +360,mfbhrbe,909,011111 ..... ..... ..... 01001 01110/,XFX7,X,,,,,BHRB,GPR,,,,,,,I,v2.07,,,Move From BHRB,X,,,, +361,mfcr,122,011111 ..... 0//// ///// 00000 10011/,XFX5,XFX,,,CR,,,GPR,,,,,,,I,P1,,,Move From CR,,,Y,Y,Y +362,mffs[.],170,111111 ..... 00000 ///// 10010 00111.,X38,X,,,,,FPSCR,FPR,CR,,,,,,I,P1,,,Move From FPSCR,X,,,, +363,mffscdrn,170,111111 ..... 10100 ..... 10010 00111/,X42,X,,,,FPR,,FPR,FPSCR,,,,,,I,v3.0B,,,Move From FPSCR Control & set DRN,X,,,, +364,mffscdrni,170,111111 ..... 10101 //... 10010 00111/,X41,X,,,,,FPSCR,FPR,,,,,,,I,v3.0B,,,Move From FPSCR Control & set DRN Immediate,X,,,, +365,mffsce,170,111111 ..... 00001 ///// 10010 00111/,X38,X,,,,,FPSCR,FPR,FPSCR,,,,,,I,v3.0B,,,Move From FPSCR & Clear Enables,X,,,, +366,mffscrn,170,111111 ..... 10110 ..... 10010 00111/,X42,X,,,,FPR,FPSCR,FPR,FPSCR,,,,,,I,v3.0B,,,Move From FPSCR Control & set RN,X,,,, +367,mffscrni,170,111111 ..... 10111 ///.. 10010 00111/,X40,X,,,,,FPSCR,FPR,FPSCR,,,,,,I,v3.0B,,,Move From FPSCR Control & set RN Immediate,X,,,, +368,mffsl,170,111111 ..... 11000 ///// 10010 00111/,X38,X,,,,,FPSCR,FPR,,,,,,,I,v3.0B,,,Move From FPSCR Lightweight,X,,,, +369,mfmsr,979,011111 ..... ///// ///// 00010 10011/,X70,X,,,,,MSR,GPR,,,,,,,III,P1,P,,Move From MSR,X,,Y,, +370,mfocrf,122,011111 ..... 1.... ..../ 00000 10011/,XFX6,XFX,,,CR,,,GPR,,,,,,,I,v2.01,,,Move From One CR Field,X,,,, +371,mfspr,119 975,011111 ..... ..... ..... 01010 10011/,XFX8,X,,MSR,,SPR,SPR,GPR,,,,,architecture/implementation-specific behavior,,X,P1,O,,Move From SPR,,,Y,,Y +372,mftb,898,011111 ..... ..... ..... 01011 10011/,XFX9,X,,,,,SPR,GPR,,,,,,,II,PPC,,,Move From Time Base,X,,,, +373,mfvscr,362,000100 ..... ///// ///// 11000 000100,VX3,VX,,,,,VSCR,VR,,,,,,,I,v2.03,,,Move From VSCR,X,,,, +374,mfvsrd,112,011111 ..... ..... ///// 00001 10011.,X80,XX1,,,VSR,GPR,MSR,GPR,,,,,,,I,v2.07,,,Move From VSR Doubleword,X,,,, +375,mfvsrld,112,011111 ..... ..... ///// 01001 10011.,X80,XX1,,,VSR,GPR,MSR,GPR,,,,,,,I,v3.0,,,Move From VSR Lower Doubleword,X,,,, +376,mfvsrwz,113,011111 ..... ..... ///// 00011 10011.,X80,XX1,,,VSR,GPR,MSR,GPR,,,,,,,I,v2.07,,,Move From VSR Word & Zero,X,,,, +377,modsd,83,011111 ..... ..... ..... 11000 01001/,X77,X,,,GPR,GPR,,GPR,,,,,,,I,v3.0,,,Modulo Signed Doubleword,,,,, +378,modsw,77,011111 ..... ..... ..... 11000 01011/,X77,X,,,GPR,GPR,,GPR,,,,,,,I,v3.0,,,Modulo Signed Word,,,Y,, +379,modud,83,011111 ..... ..... ..... 01000 01001/,X77,X,,,GPR,GPR,,GPR,,,,,,,I,v3.0,,,Modulo Unsigned Doubleword,,,Y,, +380,moduw,77,011111 ..... ..... ..... 01000 01011/,X77,X,,,GPR,GPR,,GPR,,,,,,,I,v3.0,,,Modulo Unsigned Word,,,Y,, +381,msgclr,1130,011111 ///// ///// ..... 00111 01110/,X3,X,,,,GPR,,other thread?,,,,,,,III,v2.07,HV,,Message Clear,X,,,, +382,msgclrp,1132,011111 ///// ///// ..... 00101 01110/,X3,X,,,,GPR,,SPR,,,,,,,III,v2.07,P,,Message Clear Privileged,X,,,, +383,msgsnd,1129,011111 ///// ///// ..... 00110 01110/,X3,X,,,,GPR,,other thread?,,,,,,,III,v2.07,HV,,Message Send,X,,,, +384,msgsndp,1131,011111 ///// ///// ..... 00100 01110/,X3,X,,,,GPR,,SPR,,,,,,,III,v2.07,P,,Message Send Privileged,X,,,, +385,msgsync,1132,011111 ///// ///// ///// 11011 10110/,X1,X,,,,,,,,,,,,,III,v3.0,HV,,Message Synchronize,X,,,, +386,mtcrf,121,011111 ..... 0.... ..../ 00100 10000/,XFX2,XFX,,,CR,GPR,,CR,,,,,,,I,P1,,,Move To CR Fields,,,Y,Y,Y +387,mtfsb0[.],173,111111 ..... ///// ///// 00010 00110.,X32,X,,,,,,FPSCR,CR1,,,,,,I,P1,,,Move To FPSCR Bit 0,X,,,, +388,mtfsb1[.],173,111111 ..... ///// ///// 00001 00110.,X32,X,,,,,,FPSCR,CR1,,,,,,I,P1,,,Move To FPSCR Bit 1,X,,,, +389,mtfsf[.],172,111111 ..... ..... ..... 10110 00111.,XFL1,XFL,,,,FPR,,FPSCR,CR1,,,,,,I,P1,,,Move To FPSCR Fields,X,,,, +390,mtfsfi[.],172,111111 ...// ////. ..../ 00100 00110.,X20,X,,,,,,FPSCR,CR1,,,,,,I,P1,,,Move To FPSCR Field Immediate,X,,,, +391,mtmsr,977,011111 ..... ////. ///// 00100 10010/,X56,X,,,,GPR,,MSR,,,,,,,III,P1,P,,Move To MSR,X,,,, +392,mtmsrd,978,011111 ..... ////. ///// 00101 10010/,X56,X,,,,GPR,MSR,MSR,,,,,,,III,PPC,P,,Move To MSR Doubleword,X,,Y,, +393,mtocrf,121,011111 ..... 1.... ..../ 00100 10000/,XFX3,XFX,,,,GPR,,CR,,,,,,,I,v2.01,,,Move To One CR Field,,,Y,Y,Y +394,mtvscr,362,000100 ///// ///// ..... 11001 000100,VX1,VX,,,VR,,,VSCR,,,,,,,I,v2.03,,,Move To VSCR,X,,,, +395,mtvsrd,114,011111 ..... ..... ///// 00101 10011.,X83,XX1,,,,GPR,MSR,VSR,,,,,,,I,v2.07,,,Move To VSR Doubleword,X,,,, +396,mtvsrdd,115,011111 ..... ..... ..... 01101 10011.,X84,XX1,,,GPR,GPR,MSR,VSR,,,,,,,I,v3.0,,,Move To VSR Double Doubleword,X,,,, +397,mtvsrwa,114,011111 ..... ..... ///// 00110 10011.,X83,XX1,,,,GPR,MSR,VSR,,,,,,,I,v2.07,,,Move To VSR Word Algebraic,X,,,, +398,mtvsrws,116,011111 ..... ..... ///// 01100 10011.,X83,XX1,,,,GPR,MSR,VSR,,,,,,,I,v3.0,,,Move To VSR Word & Splat,X,,,, +399,mtvsrwz,115,011111 ..... ..... ///// 00111 10011.,X83,XX1,,,,GPR,MSR,VSR,,,,,,,I,v2.07,,,Move To VSR Word & Zero,X,,,, +400,mulhd[.],79,011111 ..... ..... ..... /0010 01001.,XO3,XO,,,GPR,GPR,,GPR,CR0,,,,,,I,PPC,,SR,Multiply High Doubleword,,,Y,,Y +401,mulhdu[.],79,011111 ..... ..... ..... /0000 01001.,XO3,XO,,,GPR,GPR,,GPR,CR0,,,,,,I,PPC,,SR,Multiply High Doubleword Unsigned,,,Y,, +402,mulhw[.],73,011111 ..... ..... ..... /0010 01011.,XO3,XO,,,GPR,GPR,,GPR,CR0,,,,,,I,PPC,,SR,Multiply High Word,,,Y,, +403,mulhwu[.],73,011111 ..... ..... ..... /0000 01011.,XO3,XO,,,GPR,GPR,,GPR,CR0,,,,,,I,PPC,,SR,Multiply High Word Unsigned,,,Y,, +404,mulld[o][.],79,011111 ..... ..... ..... .0111 01001.,XO4,XO,,,GPR,GPR,,GPR,CR0,XER,,,,,I,PPC,,SR,Multiply Low Doubleword,,,Y,,Y +405,mulli,73,000111 ..... ..... ..... ..... ......,D8,D,,,,GPR,,GPR,,,,,,,I,P1,,,Multiply Low Immediate,,,Y,,Y +406,mullw[o][.],73,011111 ..... ..... ..... .0111 01011.,XO4,XO,,,GPR,GPR,,GPR,CR0,XER,,,,,I,P1,,SR,Multiply Low Word,,,Y,,Y +407,nand[.],94,011111 ..... ..... ..... 01110 11100.,X68,X,,,GPR,GPR,,GPR,CR0,,,,,,I,P1,,SR,NAND,,,Y,, +408,neg[o][.],72,011111 ..... ..... ///// .0011 01000.,XO1,XO,,,,GPR,,GPR,CR0,XER,,,,,I,P1,,SR,Negate,,,Y,,Y +409,nor[.],95,011111 ..... ..... ..... 00011 11100.,X68,X,,,GPR,GPR,,GPR,CR0,,,,,,I,P1,,SR,NOR,,,Y,,Y +410,or[.],94,011111 ..... ..... ..... 01101 11100.,X68,X,,,GPR,GPR,,GPR,CR0,,,,,,I,P1,,SR,OR,,,Y,,Y +411,orc[.],95,011111 ..... ..... ..... 01100 11100.,X68,X,,,GPR,GPR,,GPR,CR0,,,,,,I,P1,,SR,OR with Complement,,,Y,,Y +412,ori,92,011000 ..... ..... ..... ..... ......,D6,D,,,,GPR,,GPR,,,,,,,I,P1,,,OR Immediate,,,Y,,Y +413,oris,93,011001 ..... ..... ..... ..... ......,D6,D,,,,GPR,,GPR,,,,,,,I,P1,,,OR Immediate Shifted,,,Y,,Y +414,paste[.],855,011111 ////. ..... ..... 11100 00110.,X6,X,,,GPR,GPR,,CR,,,,,,,II,v3.0,,,Paste,,,,, +415,popcntb,97,011111 ..... ..... ///// 00011 11010/,X60,X,,,,GPR,,GPR,,,,,,,I,v2.02,,,Population Count Byte,,,Y,, +416,popcntd,99,011111 ..... ..... ///// 01111 11010/,X62,X,,,,GPR,,GPR,,,,,,,I,v2.06,,,Population Count Doubleword,,,Y,, +417,popcntw,97,011111 ..... ..... ///// 01011 11010/,X60,X,,,,GPR,,GPR,,,,,,,I,v2.06,,,Population Count Words,,,Y,, +418,prtyd,98,011111 ..... ..... ///// 00101 11010/,X60,X,,,,GPR,,GPR,,,,,,,I,v2.05,,,Parity Doubleword,,,Y,, +419,prtyw,98,011111 ..... ..... ///// 00100 11010/,X60,X,,,,GPR,,GPR,,,,,,,I,v2.05,,,Parity Word,,,Y,, +420,rfebb,905,010011 ///// ///// ////. 00100 10010/,XL2,XL,,,,SPR,BESCR,BESCR,MSR,NIA,,,,,I,v2.07,,,Return from Event Based Branch,X,,,, +421,rfid,955,010011 ///// ///// ///// 00000 10010/,XL1,XL,,,,SPR,MSR,MSR,NIA,,,,,,III,PPC,P,,Return from Interrupt Doubleword,X,,Y,, +422,rfscv,953,010011 ///// ///// ///// 00010 10010/,XL1,XL,,MSR,,LR,SPR,MSR,NIA,,,,,,III,v3.0,P,,Return From System Call Vectored,X,,,, +423,rldcl[.],104,011110 ..... ..... ..... ..... .1000.,MDS1,MDS,,,GPR,GPR,,GPR,CR0,,,,,,I,PPC,,SR,Rotate Left Doubleword then Clear Left,,,Y,, +424,rldcr[.],104,011110 ..... ..... ..... ..... .1001.,MDS2,MDS,,,GPR,GPR,,GPR,CR0,,,,,,I,PPC,,SR,Rotate Left Doubleword then Clear Right,,,Y,,Y +425,rldic[.],105,011110 ..... ..... ..... ..... .010..,MD1,MD,,,,GPR,,GPR,CR0,,,,,,I,PPC,,SR,Rotate Left Doubleword Immediate then Clear,,,,, +426,rldicl[.],105,011110 ..... ..... ..... ..... .000..,MD1,MD,,,,GPR,,GPR,CR0,,,,,,I,PPC,,SR,Rotate Left Doubleword Immediate then Clear Left,,,Y,,Y +427,rldicr[.],106,011110 ..... ..... ..... ..... .001..,MD2,MD,,,,GPR,,GPR,CR0,,,,,,I,PPC,,SR,Rotate Left Doubleword Immediate then Clear Right,,,Y,,Y +428,rldimi[.],106,011110 ..... ..... ..... ..... .011..,MD1,MD,,,,GPR,,GPR,CR0,,,,,,I,PPC,,SR,Rotate Left Doubleword Immediate then Mask Insert,,,Y,,Y +429,rlwimi[.],103,010100 ..... ..... ..... ..... ......,M2,M,,,,GPR,,GPR,CR0,,,,,,I,P1,,SR,Rotate Left Word Immediate then Mask Insert,,,Y,,Y +430,rlwinm[.],102,010101 ..... ..... ..... ..... ......,M2,M,,,,GPR,,GPR,CR0,,,,,,I,P1,,SR,Rotate Left Word Immediate then AND with Mask,,,Y,,Y +431,rlwnm[.],103,010111 ..... ..... ..... ..... ......,M1,M,,,GPR,GPR,,GPR,CR0,,,,,,I,P1,,SR,Rotate Left Word then AND with Mask,,,Y,, +432,setb,122,011111 ..... ...// ///// 00100 000000,X95,VX,,,CR,,,GPR,,,,,,,I,v3.0,,,Set Boolean,,,,Y, +433,slbfee.,1031,011111 ..... ///// ..... 11110 100111,X71,X,,,,GPR,SLB,GPR,CR,,,,,,III,v2.05,P,SR,SLB Find Entry ESID & record,X,,,, +434,slbia,1026,011111 //... ///// ///// 01111 10010/,X14,X,,,,,,SLB,,,,,,,III,PPC,P,,SLB Invalidate All,X,,Y,, +435,slbiag,1028,011111 ..... ///// ..... 11010 10010/,X96,X,,LPIDR,,GPR,MSR,SLB,,,,,,,III,v3.0B,P,,SLB Invalidate All Global,X,,,, +436,slbie,1024,011111 ///// ///// ..... 01101 10010/,X3,X,,,,GPR,,SLBE,,,,,,,III,PPC,P,,SLB Invalidate Entry,X,,,, +437,slbmfee,1031,011111 ..... ///// ..... 11100 10011/,X72,X,,,,GPR,SLB,GPR,,,,,,,III,v2.00,P,,SLB Move From Entry ESID,X,,,, +438,slbmfev,1030,011111 ..... ///// ..... 11010 10011/,X72,X,,,,GPR,SLB,GPR,,,,,,,III,v2.00,P,,SLB Move From Entry VSID,X,,,, +439,slbmte,1029,011111 ..... ///// ..... 01100 10010/,X55,X,,,GPR,GPR,,SLB,,,,,,,III,v2.00,P,,SLB Move To Entry,X,,,, +440,slbsync,1032,011111 ///// ///// ///// 01010 10010/,X1,X,,,,,,,,,,,,,III,v3.0,P,,SLB Synchronize,X,,,, +441,sld[.],109,011111 ..... ..... ..... 00000 11011.,X68,X,,,GPR,GPR,,GPR,CR0,,,,,,I,PPC,,SR,Shift Left Doubleword,,,Y,,Y +442,slw[.],107,011111 ..... ..... ..... 00000 11000.,X68,X,,,GPR,GPR,,GPR,CR0,,,,,,I,P1,,SR,Shift Left Word,,,Y,,Y +443,srad[.],110,011111 ..... ..... ..... 11000 11010.,X68,X,,,GPR,GPR,,GPR,XER,CR0,,,,,I,PPC,,SR,Shift Right Algebraic Doubleword,,,Y,,Y +444,sradi[.],110,011111 ..... ..... ..... 11001 1101..,XS1,XS,,,,GPR,,GPR,XER,CR0,,,,,I,PPC,,SR,Shift Right Algebraic Doubleword Immediate,,,Y,,Y +445,sraw[.],108,011111 ..... ..... ..... 11000 11000.,X68,X,,,GPR,GPR,,GPR,XER,CR0,,,,,I,P1,,SR,Shift Right Algebraic Word,,,Y,,Y +446,srawi[.],108,011111 ..... ..... ..... 11001 11000.,X65,X,,,,GPR,,GPR,XER,CR0,,,,,I,P1,,SR,Shift Right Algebraic Word Immediate,,,Y,,Y +447,srd[.],109,011111 ..... ..... ..... 10000 11011.,X68,X,,,GPR,GPR,,GPR,CR0,,,,,,I,PPC,,SR,Shift Right Doubleword,,,Y,,Y +448,srw[.],107,011111 ..... ..... ..... 10000 11000.,X68,X,,,GPR,GPR,,GPR,CR0,,,,,,I,P1,,SR,Shift Right Word,,,Y,,Y +449,stb,54,100110 ..... ..... ..... ..... ......,D5,D,,,GPR,GPR,,,,,,,,,I,P1,,,Store Byte,,,Y,,Y +450,stbcix,967,011111 ..... ..... ..... 11110 10101/,X66,X,,GPR,GPR,GPR,,,,,,,,,III,v2.05,HV,,Store Byte Caching Inhibited Indexed,X,,Y,, +451,stbu,54,100111 ..... ..... ..... ..... ......,D5,D,,,GPR,GPR,,GPR,,,,,,,I,P1,,,Store Byte with Update,,,Y,,Y +452,stbux,54,011111 ..... ..... ..... 00111 10111/,X66,X,,GPR,GPR,GPR,,GPR,,,,,,,I,P1,,,Store Byte with Update Indexed,,,Y,, +453,stbx,54,011111 ..... ..... ..... 00110 10111/,X66,X,,GPR,GPR,GPR,,,,,,,,,I,P1,,,Store Byte Indexed,,,Y,,Y +454,std,57,111110 ..... ..... ..... ..... ....00,DS3,DS,,,GPR,GPR,,,,,,,,,I,PPC,,,Store Doubleword,,,Y,,Y +455,stdat,862,011111 ..... ..... ..... 10111 00110/,X63,X,,,,GPR,,,,,,,"function code field determines behavior, including source registers",,II,v3.0,,,Store Doubleword ATomic,X,,,, +456,stdbrx,61,011111 ..... ..... ..... 10100 10100/,X66,X,,GPR,GPR,GPR,,,,,,,,,I,v2.06,,,Store Doubleword Byte-Reverse Indexed,X,,Y,, +457,stdcix,967,011111 ..... ..... ..... 11111 10101/,X66,X,,GPR,GPR,GPR,,,,,,,,,III,v2.05,HV,,Store Doubleword Caching Inhibited Indexed,X,,Y,, +458,stdu,57,111110 ..... ..... ..... ..... ....01,DS3,DS,,,GPR,GPR,,GPR,,,,,,,I,PPC,,,Store Doubleword with Update,,,Y,,Y +459,stdux,57,011111 ..... ..... ..... 00101 10101/,X66,X,,GPR,GPR,GPR,,GPR,,,,,,,I,PPC,,,Store Doubleword with Update Indexed,,,Y,, +460,stdx,57,011111 ..... ..... ..... 00100 10101/,X66,X,,GPR,GPR,GPR,,,,,,,,,I,PPC,,,Store Doubleword Indexed,,,Y,,Y +461,stfd,146,110110 ..... ..... ..... ..... ......,D3,D,,,FPR,GPR,,,,,,,,,I,P1,,,Store Floating Double,,,,, +462,stfdp,149,111101 ..... ..... ..... ..... ....00,DS1,DS,,FPR,FPR,GPR,,,,,,,,,I,v2.05,,,Store Floating Double Pair,,,,, +463,stfdu,146,110111 ..... ..... ..... ..... ......,D3,D,,,FPR,GPR,,GPR,,,,,,,I,P1,,,Store Floating Double with Update,,,,, +464,stfdux,146,011111 ..... ..... ..... 10111 10111/,X33,X,,FPR,GPR,GPR,,GPR,,,,,,,I,P1,,,Store Floating Double with Update Indexed,,,,, +465,stfdx,146,011111 ..... ..... ..... 10110 10111/,X33,X,,FPR,GPR,GPR,,,,,,,,,I,P1,,,Store Floating Double Indexed,,,,, +466,stfiwx,147,011111 ..... ..... ..... 11110 10111/,X33,X,,FPR,GPR,GPR,,,,,,,,,I,PPC,,,Store Floating as Integer Word Indexed,,,,, +467,stfs,145,110100 ..... ..... ..... ..... ......,D3,D,,,FPR,GPR,,,,,,,,,I,P1,,,Store Floating Single,,,,, +468,stfsu,145,110101 ..... ..... ..... ..... ......,D3,D,,,FPR,GPR,,GPR,,,,,,,I,P1,,,Store Floating Single with Update,,,,, +469,stfsux,145,011111 ..... ..... ..... 10101 10111/,X33,X,,FPR,GPR,GPR,,GPR,,,,,,,I,P1,,,Store Floating Single with Update Indexed,,,,, +470,stfsx,145,011111 ..... ..... ..... 10100 10111/,X33,X,,FPR,GPR,GPR,,,,,,,,,I,P1,,,Store Floating Single Indexed,,,,, +471,sth,55,101100 ..... ..... ..... ..... ......,D5,D,,,GPR,GPR,,,,,,,,,I,P1,,,Store Halfword,,,Y,,Y +472,sthbrx,60,011111 ..... ..... ..... 11100 10110/,X66,X,,GPR,GPR,GPR,,,,,,,,,I,P1,,,Store Halfword Byte-Reverse Indexed,X,,Y,, +473,sthcix,967,011111 ..... ..... ..... 11101 10101/,X66,X,,GPR,GPR,GPR,,,,,,,,,III,v2.05,HV,,Store Halfword Caching Inhibited Indexed,X,,Y,, +474,sthu,55,101101 ..... ..... ..... ..... ......,D5,D,,,GPR,GPR,,GPR,,,,,,,I,P1,,,Store Halfword with Update,,,Y,,Y +475,sthux,55,011111 ..... ..... ..... 01101 10111/,X66,X,,GPR,GPR,GPR,,GPR,,,,,,,I,P1,,,Store Halfword with Update Indexed,,,Y,, +476,sthx,55,011111 ..... ..... ..... 01100 10111/,X66,X,,GPR,GPR,GPR,,,,,,,,,I,P1,,,Store Halfword Indexed,,,Y,,Y +477,stmw,62,101111 ..... ..... ..... ..... ......,D5,D,,,,GPR,,,,,,,GPRs [31-RS:31] are stored,,I,P1,,,Store Multiple Word,X,,,, +478,stop,958,010011 ///// ///// ///// 01011 10010/,XL1,XL,,,,SPR,MSR,,,,,,,,III,v3.0,P,,Stop,,,,, +479,stq,59,111110 ..... ..... ..... ..... ....10,DS4,DS,,GPR,GPR,GPR,,,,,,,,,I,v2.03,,,Store Quadword,,,,, +480,stswi,65,011111 ..... ..... ..... 10110 10101/,X64,X,,,,GPR,,,,,,,,,I,P1,,,Store String Word Immediate,,,,, +481,stvebx,245,011111 ..... ..... ..... 00100 00111/,X89,X,,VR,GPR,GPR,,,,,,,,,I,v2.03,,,Store Vector Element Byte Indexed,,,,, +482,stvehx,245,011111 ..... ..... ..... 00101 00111/,X89,X,,VR,GPR,GPR,,,,,,,,,I,v2.03,,,Store Vector Element Halfword Indexed,,,,, +483,stvewx,246,011111 ..... ..... ..... 00110 00111/,X89,X,,VR,GPR,GPR,,,,,,,,,I,v2.03,,,Store Vector Element Word Indexed,,,,, +484,stvx,246,011111 ..... ..... ..... 00111 00111/,X89,X,,VR,GPR,GPR,,,,,,,,,I,v2.03,,,Store Vector Indexed,,,,, +485,stvxl,246,011111 ..... ..... ..... 01111 00111/,X89,X,,VR,GPR,GPR,,,,,,,,,I,v2.03,,,Store Vector Indexed Last,,,,, +486,stw,56,100100 ..... ..... ..... ..... ......,D5,D,,,GPR,GPR,,,,,,,,,I,P1,,,Store Word,,,Y,,Y +487,stwat,862,011111 ..... ..... ..... 10110 00110/,X63,X,,,,GPR,,,,,,,"function code field determines behavior, including source registers",,II,v3.0,,,Store Word ATomic,X,,,, +488,stwbrx,60,011111 ..... ..... ..... 10100 10110/,X66,X,,GPR,GPR,GPR,,,,,,,,,I,P1,,,Store Word Byte-Reverse Indexed,X,,Y,, +489,stwcix,967,011111 ..... ..... ..... 11100 10101/,X66,X,,GPR,GPR,GPR,,,,,,,,,III,v2.05,HV,,Store Word Caching Inhibited Indexed,X,,Y,, +490,stwu,56,100101 ..... ..... ..... ..... ......,D5,D,,,GPR,GPR,,GPR,,,,,,,I,P1,,,Store Word with Update,,,Y,,Y +491,stwux,56,011111 ..... ..... ..... 00101 10111/,X66,X,,GPR,GPR,GPR,,GPR,,,,,,,I,P1,,,Store Word with Update Indexed,,,Y,, +492,stwx,56,011111 ..... ..... ..... 00100 10111/,X66,X,,GPR,GPR,GPR,,,,,,,,,I,P1,,,Store Word Indexed,,,Y,,Y +493,stxsd,498,111101 ..... ..... ..... ..... ....10,DS6,DS,,,VSR,GPR,MSR,,,,,,,,I,v3.0,,,Store VSX Scalar Doubleword,,,,, +494,stxssp,501,111101 ..... ..... ..... ..... ....11,DS6,DS,,,VSR,GPR,MSR,,,,,,,,I,v3.0,,,Store VSX Scalar Single-Precision,,,,, +495,stxv,507,111101 ..... ..... ..... ..... ...101,DQ2,DQ,,,VSR,GPR,MSR,,,,,,,,I,v3.0,,,Store VSX Vector,,,,, +496,subf[o][.],69,011111 ..... ..... ..... .0001 01000.,XO4,XO,,,GPR,GPR,,GPR,CR0,XER,,,,,I,PPC,,SR,Subtract From,,,Y,,Y +497,subfc[o][.],70,011111 ..... ..... ..... .0000 01000.,XO4,XO,,,GPR,GPR,,GPR,XER,CR0,,,,,I,P1,,SR,Subtract From Carrying,,,Y,,Y +498,subfe[o][.],71,011111 ..... ..... ..... .0100 01000.,XO4,XO,,,GPR,GPR,XER,GPR,XER,CR0,,,,,I,P1,,SR,Subtract From Extended,,,Y,,Y +499,subfic,70,001000 ..... ..... ..... ..... ......,D8,D,,,,GPR,,GPR,XER,,,,,,I,P1,,SR,Subtract From Immediate Carrying,,,Y,,Y +500,subfme[o][.],71,011111 ..... ..... ///// .0111 01000.,XO1,XO,,,,GPR,XER,GPR,XER,CR0,,,,,I,P1,,SR,Subtract From Minus One Extended,,,Y,, +501,subfze[o][.],72,011111 ..... ..... ///// .0110 01000.,XO1,XO,,,,GPR,XER,GPR,XER,CR0,,,,,I,P1,,SR,Subtract From Zero Extended,,,Y,, +502,sync,873,011111 ///.. ///// ///// 10010 10110/,X11,X,,,,,,,,,,,,,II,P1,,,Synchronize,X,,Y,, +503,tcheck,895,011111 ...// ///// ///// 10110 01110/,X18,X,,TDOOMED,,SPR,MSR,CR,,,,,,,II,v2.07,,,Transaction Check & record,X,,,, +504,td,91,011111 ..... ..... ..... 00010 00100/,X87,X,,,GPR,GPR,,,,,,,can invoke system trap handler,Y on trap,I,PPC,,,Trap Doubleword,X,,Y,, +505,tdi,91,000010 ..... ..... ..... ..... ......,D9,D,,,,GPR,,,,,,,can invoke system trap handler,Y on trap,I,PPC,,,Trap Doubleword Immediate,X,,Y,, +506,tend.,891,011111 .//// ///// ///// 10101 01110/,X16,X,,TDOOMED,,SPR,MSR,CR,SPR,MSR,,,,,II,v2.07,,,Transaction End & record,X,,,, +507,tlbiel,1038,011111 ..... /.... ..... 01000 10010/,X57,X,,,GPR,GPR,LPIDR,TLB,,,,,,,III,v2.03,P,64,TLB Invalidate Entry Local,X,,Y,, +508,tlbsync,1042,011111 ///// ///// ///// 10001 10110/,X1,X,,,,,,,,,,,,,III,PPC,HV/P,,TLB Synchronize,X,,,, +509,trechkpt.,970,011111 ///// ///// ///// 11111 011101,X2,X,,,,SPR,MSR,CR,MSR,TDOOMED,,,,,II,v2.07,,,Transaction Recheckpoint & record,X,,,, +510,tsr.,895,011111 ////. ///// ///// 10111 01110/,X7,X,,,,,MSR,CR,MSR,,,,,,II,v2.07,,,Transaction Suspend or Resume & record,X,,,, +511,tw,90,011111 ..... ..... ..... 00000 00100/,X87,X,,,GPR,GPR,,,,,,,can invoke system trap handler,Y on trap,I,P1,,,Trap Word,X,,Y,, +512,twi,90,000011 ..... ..... ..... ..... ......,D9,D,,,,GPR,,,,,,,can invoke system trap handler,Y on trap,I,P1,,,Trap Word Immediate,X,,Y,, +513,vabsdub,297,000100 ..... ..... ..... 10000 000011,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Absolute Difference Unsigned Byte,,,,, +514,vabsduh,297,000100 ..... ..... ..... 10001 000011,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Absolute Difference Unsigned Halfword,,,,, +515,vabsduw,298,000100 ..... ..... ..... 10010 000011,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Absolute Difference Unsigned Word,,,,, +516,vaddcuq,273,000100 ..... ..... ..... 00101 000000,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Add & write Carry Unsigned Quadword,,,,, +517,vaddcuw,269,000100 ..... ..... ..... 00110 000000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Add & Write Carry-Out Unsigned Word,,,,, +518,vaddfp,321,000100 ..... ..... ..... 00000 001010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Add Floating-Point,,,,, +519,vaddsbs,269,000100 ..... ..... ..... 01100 000000,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Add Signed Byte Saturate,,,,, +520,vaddshs,269,000100 ..... ..... ..... 01101 000000,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Add Signed Halfword Saturate,,,,, +521,vaddsws,270,000100 ..... ..... ..... 01110 000000,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Add Signed Word Saturate,,,,, +522,vaddubm,270,000100 ..... ..... ..... 00000 000000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Add Unsigned Byte Modulo,,,,, +523,vaddubs,272,000100 ..... ..... ..... 01000 000000,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Add Unsigned Byte Saturate,,,,, +524,vaddudm,270,000100 ..... ..... ..... 00011 000000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Add Unsigned Doubleword Modulo,,,,, +525,vadduhm,271,000100 ..... ..... ..... 00001 000000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Add Unsigned Halfword Modulo,,,,, +526,vadduhs,272,000100 ..... ..... ..... 01001 000000,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Add Unsigned Halfword Saturate,,,,, +527,vadduqm,273,000100 ..... ..... ..... 00100 000000,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Add Unsigned Quadword Modulo,,,,, +528,vadduwm,271,000100 ..... ..... ..... 00010 000000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Add Unsigned Word Modulo,,,,, +529,vadduws,272,000100 ..... ..... ..... 01010 000000,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Add Unsigned Word Saturate,,,,, +530,vand,312,000100 ..... ..... ..... 10000 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Logical AND,,,,, +531,vandc,312,000100 ..... ..... ..... 10001 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Logical AND with Complement,,,,, +532,vavgsb,295,000100 ..... ..... ..... 10100 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Average Signed Byte,,,,, +533,vavgsh,295,000100 ..... ..... ..... 10101 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Average Signed Halfword,,,,, +534,vavgsw,295,000100 ..... ..... ..... 10110 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Average Signed Word,,,,, +535,vavgub,296,000100 ..... ..... ..... 10000 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Average Unsigned Byte,,,,, +536,vavguh,296,000100 ..... ..... ..... 10001 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Average Unsigned Halfword,,,,, +537,vavguw,296,000100 ..... ..... ..... 10010 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Average Unsigned Word,,,,, +538,vbpermd,346,000100 ..... ..... ..... 10111 001100,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Bit Permute Doubleword,,,,, +539,vbpermq,346,000100 ..... ..... ..... 10101 001100,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Bit Permute Quadword,,,,, +540,vcfsx,325,000100 ..... ..... ..... 01101 001010,VX13,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Convert with round to nearest Signed Word format to FP,,,,, +541,vcfux,325,000100 ..... ..... ..... 01100 001010,VX13,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Convert with round to nearest Unsigned Word format to FP,,,,, +542,vcipher,333,000100 ..... ..... ..... 10100 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector AES Cipher,,,,, +543,vcipherlast,333,000100 ..... ..... ..... 10100 001001,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector AES Cipher Last,,,,, +544,vclzb,340,000100 ..... ///// ..... 11100 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Count Leading Zeros Byte,,,,, +545,vclzd,340,000100 ..... ///// ..... 11111 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Count Leading Zeros Doubleword,,,,, +546,vclzh,340,000100 ..... ///// ..... 11101 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Count Leading Zeros Halfword,,,,, +547,vclzlsbb,342,000100 ..... 00000 ..... 11000 000010,VX2,VX,,,VR,,MSR,GPR,,,,,,,I,v3.0,,,Vector Count Leading Zero Least-Significant Bits Byte,,,,, +548,vclzw,340,000100 ..... ///// ..... 11110 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Count Leading Zeros Word,,,,, +549,vcmpbfp[.],328,000100 ..... ..... ..... .1111 000110,VC1,VC,,VR,VR,,,VR,CR,,,,,,I,v2.03,,,Vector Compare Bounds Floating-Point,,,,, +550,vcmpeqfp[.],329,000100 ..... ..... ..... .0011 000110,VC1,VC,,VR,VR,,,VR,CR,,,,,,I,v2.03,,,Vector Compare Equal To Floating-Point,,,,, +551,vcmpequb[.],303,000100 ..... ..... ..... .0000 000110,VC1,VC,,VR,VR,,,VR,CR,,,,,,I,v2.03,,,Vector Compare Equal To Unsigned Byte,,,,, +552,vcmpequd[.],304,000100 ..... ..... ..... .0011 000111,VC1,VC,,VR,VR,,,VR,CR,,,,,,I,v2.07,,,Vector Compare Equal To Unsigned Doubleword,,,,, +553,vcmpequh[.],303,000100 ..... ..... ..... .0001 000110,VC1,VC,,VR,VR,,,VR,CR,,,,,,I,v2.03,,,Vector Compare Equal To Unsigned Halfword,,,,, +554,vcmpequw[.],304,000100 ..... ..... ..... .0010 000110,VC1,VC,,VR,VR,,,VR,CR,,,,,,I,v2.03,,,Vector Compare Equal To Unsigned Word,,,,, +555,vcmpgefp[.],329,000100 ..... ..... ..... .0111 000110,VC1,VC,,VR,VR,,,VR,CR,,,,,,I,v2.03,,,Vector Compare Greater Than or Equal To Floating-Point,,,,, +556,vcmpgtfp[.],330,000100 ..... ..... ..... .1011 000110,VC1,VC,,VR,VR,,,VR,CR,,,,,,I,v2.03,,,Vector Compare Greater Than Floating-Point,,,,, +557,vcmpgtsb[.],305,000100 ..... ..... ..... .1100 000110,VC1,VC,,VR,VR,,,VR,CR,,,,,,I,v2.03,,,Vector Compare Greater Than Signed Byte,,,,, +558,vcmpgtsd[.],305,000100 ..... ..... ..... .1111 000111,VC1,VC,,VR,VR,,,VR,CR,,,,,,I,v2.07,,,Vector Compare Greater Than Signed Doubleword,,,,, +559,vcmpgtsh[.],306,000100 ..... ..... ..... .1101 000110,VC1,VC,,VR,VR,,,VR,CR,,,,,,I,v2.03,,,Vector Compare Greater Than Signed Halfword,,,,, +560,vcmpgtsw[.],306,000100 ..... ..... ..... .1110 000110,VC1,VC,,VR,VR,,,VR,CR,,,,,,I,v2.03,,,Vector Compare Greater Than Signed Word,,,,, +561,vcmpgtub[.],307,000100 ..... ..... ..... .1000 000110,VC1,VC,,VR,VR,,,VR,CR,,,,,,I,v2.03,,,Vector Compare Greater Than Unsigned Byte,,,,, +562,vcmpgtud[.],307,000100 ..... ..... ..... .1011 000111,VC1,VC,,VR,VR,,,VR,CR,,,,,,I,v2.07,,,Vector Compare Greater Than Unsigned Doubleword,,,,, +563,vcmpgtuh[.],308,000100 ..... ..... ..... .1001 000110,VC1,VC,,VR,VR,,,VR,CR,,,,,,I,v2.03,,,Vector Compare Greater Than Unsigned Halfword,,,,, +564,vcmpgtuw[.],308,000100 ..... ..... ..... .1010 000110,VC1,VC,,VR,VR,,,VR,CR,,,,,,I,v2.03,,,Vector Compare Greater Than Unsigned Word,,,,, +565,vcmpneb[.],309,000100 ..... ..... ..... .0000 000111,VC1,VC,,VR,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Vector Compare Not Equal Byte,,,,, +566,vcmpneh[.],310,000100 ..... ..... ..... .0001 000111,VC1,VC,,VR,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Vector Compare Not Equal Halfword,,,,, +567,vcmpnew[.],311,000100 ..... ..... ..... .0010 000111,VC1,VC,,VR,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Vector Compare Not Equal Word,,,,, +568,vcmpnezb[.],309,000100 ..... ..... ..... .0100 000111,VC1,VC,,VR,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Vector Compare Not Equal or Zero Byte,,,,, +569,vcmpnezh[.],310,000100 ..... ..... ..... .0101 000111,VC1,VC,,VR,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Vector Compare Not Equal or Zero Halfword,,,,, +570,vcmpnezw[.],311,000100 ..... ..... ..... .0110 000111,VC1,VC,,VR,VR,,MSR,VR,CR,,,,,,I,v3.0,,,Vector Compare Not Equal or Zero Word,,,,, +571,vctsxs,324,000100 ..... ..... ..... 01111 001010,VX13,VX,,,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Convert with round to zero FP To Signed Word format Saturate,,,,, +572,vctuxs,324,000100 ..... ..... ..... 01110 001010,VX13,VX,,,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Convert with round to zero FP To Unsigned Word format Saturate,,,,, +573,vctzb,341,000100 ..... 11100 ..... 11000 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Count Trailing Zeros Byte,,,,, +574,vctzd,341,000100 ..... 11111 ..... 11000 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Count Trailing Zeros Doubleword,,,,, +575,vctzh,341,000100 ..... 11101 ..... 11000 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Count Trailing Zeros Halfword,,,,, +576,vctzlsbb,342,000100 ..... 00001 ..... 11000 000010,VX2,VX,,,VR,,MSR,GPR,,,,,,,I,v3.0,,,Vector Count Trailing Zero Least-Significant Bits Byte,,,,, +577,vctzw,341,000100 ..... 11110 ..... 11000 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Count Trailing Zeros Word,,,,, +578,veqv,312,000100 ..... ..... ..... 11010 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Equivalence,,,,, +579,vexptefp,331,000100 ..... ///// ..... 00110 001010,VX4,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector 2 Raised to the Exponent Estimate Floating-Point,,,,, +580,vextractd,267,000100 ..... /.... ..... 01011 001101,VX7,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Extract Doubleword,,,,, +581,vextractub,267,000100 ..... /.... ..... 01000 001101,VX7,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Extract Unsigned Byte,,,,, +582,vextractuh,267,000100 ..... /.... ..... 01001 001101,VX7,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Extract Unsigned Halfword,,,,, +583,vextractuw,267,000100 ..... /.... ..... 01010 001101,VX7,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Extract Unsigned Word,,,,, +584,vextsb2d,294,000100 ..... 11000 ..... 11000 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Extend Sign Byte to Doubleword,,,,, +585,vextsb2w,294,000100 ..... 10000 ..... 11000 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Extend Sign Byte to Word,,,,, +586,vextsh2d,294,000100 ..... 11001 ..... 11000 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Extend Sign Halfword to Doubleword,,,,, +587,vextsh2w,294,000100 ..... 10001 ..... 11000 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Extend Sign Halfword to Word,,,,, +588,vextsw2d,294,000100 ..... 11010 ..... 11000 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Extend Sign Word to Doubleword,,,,, +589,vextublx,343,000100 ..... ..... ..... 11000 001101,VX19,VX,,,VR,GPR,MSR,GPR,,,,,,,I,v3.0,,,Vector Extract Unsigned Byte Left-Indexed,,,,, +590,vextubrx,343,000100 ..... ..... ..... 11100 001101,VX19,VX,,,VR,GPR,MSR,GPR,,,,,,,I,v3.0,,,Vector Extract Unsigned Byte Right-Indexed,,,,, +591,vextuhlx,343,000100 ..... ..... ..... 11001 001101,VX19,VX,,,VR,GPR,MSR,GPR,,,,,,,I,v3.0,,,Vector Extract Unsigned Halfword Left-Indexed,,,,, +592,vextuhrx,343,000100 ..... ..... ..... 11101 001101,VX19,VX,,,VR,GPR,MSR,GPR,,,,,,,I,v3.0,,,Vector Extract Unsigned Halfword Right-Indexed,,,,, +593,vextuwlx,344,000100 ..... ..... ..... 11010 001101,VX19,VX,,,VR,GPR,MSR,GPR,,,,,,,I,v3.0,,,Vector Extract Unsigned Word Left-Indexed,,,,, +594,vextuwrx,344,000100 ..... ..... ..... 11110 001101,VX19,VX,,,VR,GPR,MSR,GPR,,,,,,,I,v3.0,,,Vector Extract Unsigned Word Right-Indexed,,,,, +595,vgbbd,339,000100 ..... ///// ..... 10100 001100,VX4,VX,,,VR,,,VR,,,,,,,I,v2.07,,,Vector Gather Bits by Byte by Doubleword,,,,, +596,vinsertb,268,000100 ..... /.... ..... 01100 001101,VX7,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Insert Byte,,,,, +597,vinsertd,268,000100 ..... /.... ..... 01111 001101,VX7,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Insert Doubleword,,,,, +598,vinserth,268,000100 ..... /.... ..... 01101 001101,VX7,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Insert Halfword,,,,, +599,vinsertw,268,000100 ..... /.... ..... 01110 001101,VX7,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Insert Word,,,,, +600,vlogefp,331,000100 ..... ..... ..... 00111 001010,VX4,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Log Base 2 Estimate Floating-Point,,,,, +601,vmaddfp,322,000100 ..... ..... ..... ..... 101110,VA3,VA,VR,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Multiply-Add Floating-Point,,,,, +602,vmaxfp,323,000100 ..... ..... ..... 10000 001010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Maximum Floating-Point,,,,, +603,vmaxsb,299,000100 ..... ..... ..... 00100 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Maximum Signed Byte,,,,, +604,vmaxsd,299,000100 ..... ..... ..... 00111 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Maximum Signed Doubleword,,,,, +605,vmaxsh,300,000100 ..... ..... ..... 00101 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Maximum Signed Halfword,,,,, +606,vmaxsw,300,000100 ..... ..... ..... 00110 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Maximum Signed Word,,,,, +607,vmaxub,299,000100 ..... ..... ..... 00000 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Maximum Unsigned Byte,,,,, +608,vmaxud,299,000100 ..... ..... ..... 00011 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Maximum Unsigned Doubleword,,,,, +609,vmaxuh,300,000100 ..... ..... ..... 00001 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Maximum Unsigned Halfword,,,,, +610,vmaxuw,300,000100 ..... ..... ..... 00010 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Maximum Unsigned Word,,,,, +611,vmhaddshs,285,000100 ..... ..... ..... ..... 100000,VA3,VA,VR,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Multiply-High-Add Signed Halfword Saturate,,,,, +612,vmhraddshs,285,000100 ..... ..... ..... ..... 100001,VA3,VA,VR,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Multiply-High-Round-Add Signed Halfword Saturate,,,,, +613,vminfp,323,000100 ..... ..... ..... 10001 001010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Minimum Floating-Point,,,,, +614,vminsb,301,000100 ..... ..... ..... 01100 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Minimum Signed Byte,,,,, +615,vminsd,301,000100 ..... ..... ..... 01111 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Minimum Signed Doubleword,,,,, +616,vminsh,302,000100 ..... ..... ..... 01101 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Minimum Signed Halfword,,,,, +617,vminsw,302,000100 ..... ..... ..... 01110 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Minimum Signed Word,,,,, +618,vminub,301,000100 ..... ..... ..... 01000 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Minimum Unsigned Byte,,,,, +619,vminud,301,000100 ..... ..... ..... 01011 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Minimum Unsigned Doubleword,,,,, +620,vminuh,302,000100 ..... ..... ..... 01001 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Minimum Unsigned Halfword,,,,, +621,vminuw,302,000100 ..... ..... ..... 01010 000010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Minimum Unsigned Word,,,,, +622,vmladduhm,286,000100 ..... ..... ..... ..... 100010,VA3,VA,VR,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Multiply-Low-Add Unsigned Halfword Modulo,,,,, +623,vmrgew,257,000100 ..... ..... ..... 11110 001100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Merge Even Word,,,,, +624,vmrghb,255,000100 ..... ..... ..... 00000 001100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Merge High Byte,,,,, +625,vmrghh,255,000100 ..... ..... ..... 00001 001100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Merge High Halfword,,,,, +626,vmrghw,256,000100 ..... ..... ..... 00010 001100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Merge High Word,,,,, +627,vmrglb,255,000100 ..... ..... ..... 00100 001100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Merge Low Byte,,,,, +628,vmrglh,255,000100 ..... ..... ..... 00101 001100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Merge Low Halfword,,,,, +629,vmrglw,256,000100 ..... ..... ..... 00110 001100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Merge Low Word,,,,, +630,vmrgow,257,000100 ..... ..... ..... 11010 001100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Merge Odd Word,,,,, +631,vmsummbm,287,000100 ..... ..... ..... ..... 100101,VA3,VA,VR,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Multiply-Sum Mixed Byte Modulo,,,,, +632,vmsumshm,287,000100 ..... ..... ..... ..... 101000,VA3,VA,VR,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Multiply-Sum Signed Halfword Modulo,,,,, +633,vmsumshs,288,000100 ..... ..... ..... ..... 101001,VA3,VA,VR,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Multiply-Sum Signed Halfword Saturate,,,,, +634,vmsumubm,286,000100 ..... ..... ..... ..... 100100,VA3,VA,VR,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Multiply-Sum Unsigned Byte Modulo,,,,, +635,vmsumudm,289,000100 ..... ..... ..... ..... 100011,VA3,VA,VR,VR,VR,,,VR,,,,,,,I,v3.0B,,,Vector Multiply-Sum Unsigned Doubleword Modulo,,,,, +636,vmsumuhm,288,000100 ..... ..... ..... ..... 100110,VA3,VA,VR,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Multiply-Sum Unsigned Halfword Modulo,,,,, +637,vmsumuhs,289,000100 ..... ..... ..... ..... 100111,VA3,VA,VR,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Multiply-Sum Unsigned Halfword Saturate,,,,, +638,vmul10cuq,355,000100 ..... ..... ///// 00000 000001,VX14,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Multiply-by-10 & write Carry Unsigned Quadword,,,,, +639,vmul10ecuq,355,000100 ..... ..... ..... 00001 000001,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Multiply-by-10 Extended & write Carry Unsigned Quadword,,,,, +640,vmul10euq,355,000100 ..... ..... ..... 01001 000001,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Multiply-by-10 Extended Unsigned Quadword,,,,, +641,vmul10uq,355,000100 ..... ..... ///// 01000 000001,VX14,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Multiply-by-10 Unsigned Quadword,,,,, +642,vmulesb,281,000100 ..... ..... ..... 01100 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Multiply Even Signed Byte,,,,, +643,vmulesh,282,000100 ..... ..... ..... 01101 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Multiply Even Signed Halfword,,,,, +644,vmulesw,283,000100 ..... ..... ..... 01110 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Multiply Even Signed Word,,,,, +645,vmuleub,281,000100 ..... ..... ..... 01000 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Multiply Even Unsigned Byte,,,,, +646,vmuleuh,282,000100 ..... ..... ..... 01001 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Multiply Even Unsigned Halfword,,,,, +647,vmuleuw,283,000100 ..... ..... ..... 01010 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Multiply Even Unsigned Word,,,,, +648,vmulosb,281,000100 ..... ..... ..... 00100 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Multiply Odd Signed Byte,,,,, +649,vmulosh,282,000100 ..... ..... ..... 00101 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Multiply Odd Signed Halfword,,,,, +650,vmulosw,283,000100 ..... ..... ..... 00110 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Multiply Odd Signed Word,,,,, +651,vmuloub,281,000100 ..... ..... ..... 00000 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Multiply Odd Unsigned Byte,,,,, +652,vmulouh,282,000100 ..... ..... ..... 00001 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Multiply Odd Unsigned Halfword,,,,, +653,vmulouw,283,000100 ..... ..... ..... 00010 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Multiply Odd Unsigned Word,,,,, +654,vmuluwm,284,000100 ..... ..... ..... 00010 001001,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Multiply Unsigned Word Modulo,,,,, +655,vnand,312,000100 ..... ..... ..... 10110 000100,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector NAND,,,,, +656,vncipher,334,000100 ..... ..... ..... 10101 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector AES Inverse Cipher,,,,, +657,vncipherlast,334,000100 ..... ..... ..... 10101 001001,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector AES Inverse Cipher Last,,,,, +658,vnegd,293,000100 ..... 00111 ..... 11000 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Negate Doubleword,,,,, +659,vnegw,293,000100 ..... 00110 ..... 11000 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Negate Word,,,,, +660,vnmsubfp,322,000100 ..... ..... ..... ..... 101111,VA3,VA,VR,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Negative Multiply-Subtract Floating-Point,,,,, +661,vnor,313,000100 ..... ..... ..... 10100 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Logical NOR,,,,, +662,vor,313,000100 ..... ..... ..... 10010 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Logical OR,,,,, +663,vorc,313,000100 ..... ..... ..... 10101 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector OR with Complement,,,,, +664,vpermxor,338,000100 ..... ..... ..... ..... 101101,VA3,VA,VR,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Permute & Exclusive-OR,,,,, +665,vpkpx,248,000100 ..... ..... ..... 01100 001110,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Pack Pixel,,,,, +666,vpksdss,248,000100 ..... ..... ..... 10111 001110,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.07,,,Vector Pack Signed Doubleword Signed Saturate,,,,, +667,vpksdus,249,000100 ..... ..... ..... 10101 001110,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.07,,,Vector Pack Signed Doubleword Unsigned Saturate,,,,, +668,vpkshss,249,000100 ..... ..... ..... 00110 001110,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Pack Signed Halfword Signed Saturate,,,,, +669,vpkshus,250,000100 ..... ..... ..... 00100 001110,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Pack Signed Halfword Unsigned Saturate,,,,, +670,vpkswss,250,000100 ..... ..... ..... 00111 001110,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Pack Signed Word Signed Saturate,,,,, +671,vpkswus,251,000100 ..... ..... ..... 00101 001110,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Pack Signed Word Unsigned Saturate,,,,, +672,vpkudum,251,000100 ..... ..... ..... 10001 001110,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Pack Unsigned Doubleword Unsigned Modulo,,,,, +673,vpkudus,251,000100 ..... ..... ..... 10011 001110,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.07,,,Vector Pack Unsigned Doubleword Unsigned Saturate,,,,, +674,vpkuhum,251,000100 ..... ..... ..... 00000 001110,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Pack Unsigned Halfword Unsigned Modulo,,,,, +675,vpkuhus,252,000100 ..... ..... ..... 00010 001110,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Pack Unsigned Halfword Unsigned Saturate,,,,, +676,vpkuwum,252,000100 ..... ..... ..... 00001 001110,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Pack Unsigned Word Unsigned Modulo,,,,, +677,vpkuwus,252,000100 ..... ..... ..... 00011 001110,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Pack Unsigned Word Unsigned Saturate,,,,, +678,vpmsumb,336,000100 ..... ..... ..... 10000 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Polynomial Multiply-Sum Byte,,,,, +679,vpmsumd,336,000100 ..... ..... ..... 10011 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Polynomial Multiply-Sum Doubleword,,,,, +680,vpmsumh,337,000100 ..... ..... ..... 10001 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Polynomial Multiply-Sum Halfword,,,,, +681,vpmsumw,337,000100 ..... ..... ..... 10010 001000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Polynomial Multiply-Sum Word,,,,, +682,vpopcntb,345,000100 ..... ///// ..... 11100 000011,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Population Count Byte,,,,, +683,vpopcntd,345,000100 ..... ///// ..... 11111 000011,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Population Count Doubleword,,,,, +684,vpopcnth,345,000100 ..... ///// ..... 11101 000011,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Population Count Halfword,,,,, +685,vpopcntw,345,000100 ..... ///// ..... 11110 000011,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Population Count Word,,,,, +686,vprtybd,314,000100 ..... 01001 ..... 11000 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Parity Byte Doubleword,,,,, +687,vprtybq,314,000100 ..... 01010 ..... 11000 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Parity Byte Quadword,,,,, +688,vprtybw,314,000100 ..... 01000 ..... 11000 000010,VX4,VX,,,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Parity Byte Word,,,,, +689,vrefp,332,000100 ..... ///// ..... 00100 001010,VX4,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Reciprocal Estimate Floating-Point,,,,, +690,vrfim,326,000100 ..... ///// ..... 01011 001010,VX4,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Round to Floating-Point Integral toward -Infinity,,,,, +691,vrfin,326,000100 ..... ///// ..... 01000 001010,VX4,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Round to Floating-Point Integral Nearest,,,,, +692,vrfip,326,000100 ..... ///// ..... 01010 001010,VX4,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Round to Floating-Point Integral toward +Infinity,,,,, +693,vrfiz,327,000100 ..... ///// ..... 01001 001010,VX4,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Round to Floating-Point Integral toward Zero,,,,, +694,vrlb,315,000100 ..... ..... ..... 00000 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Rotate Left Byte,,,,, +695,vrld,315,000100 ..... ..... ..... 00011 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Rotate Left Doubleword,,,,, +696,vrldmi,320,000100 ..... ..... ..... 00011 000101,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Rotate Left Doubleword then Mask Insert,,,,, +697,vrldnm,320,000100 ..... ..... ..... 00111 000101,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Rotate Left Doubleword then AND with Mask,,,,, +698,vrlh,315,000100 ..... ..... ..... 00001 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Rotate Left Halfword,,,,, +699,vrlw,315,000100 ..... ..... ..... 00010 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Rotate Left Word,,,,, +700,vrlwmi,319,000100 ..... ..... ..... 00010 000101,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Rotate Left Word then Mask Insert,,,,, +701,vrlwnm,319,000100 ..... ..... ..... 00110 000101,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Rotate Left Word then AND with Mask,,,,, +702,vrsqrtefp,332,000100 ..... ///// ..... 00101 001010,VX4,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Reciprocal Square Root Estimate Floating-Point,,,,, +703,vsbox,334,000100 ..... ..... ///// 10111 001000,VX14,VX,,,VR,,,VR,,,,,,,I,v2.07,,,Vector AES S-Box,,,,, +704,vshasigmad,335,000100 ..... ..... ..... 11011 000010,VX18,VX,,,VR,,,VR,,,,,,,I,v2.07,,,Vector SHA-512 Sigma Doubleword,,,,, +705,vshasigmaw,335,000100 ..... ..... ..... 11010 000010,VX18,VX,,,VR,,,VR,,,,,,,I,v2.07,,,Vector SHA-256 Sigma Word,,,,, +706,vsl,264,000100 ..... ..... ..... 00111 000100,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v2.03,,,Vector Shift Left,,,,, +707,vslb,316,000100 ..... ..... ..... 00100 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Shift Left Byte,,,,, +708,vsld,316,000100 ..... ..... ..... 10111 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Shift Left Doubleword,,,,, +709,vsldoi,263,000100 ..... ..... ..... /.... 101100,VA2,VA,,VR,VR,,MSR,VR,,,,,,,I,v2.03,,,Vector Shift Left Double by Octet Immediate,,,,, +710,vslh,316,000100 ..... ..... ..... 00101 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Shift Left Halfword,,,,, +711,vslo,264,000100 ..... ..... ..... 10000 001100,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v2.03,,,Vector Shift Left by Octet,,,,, +712,vslv,265,000100 ..... ..... ..... 11101 000100,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Shift Left Variable,,,,, +713,vslw,316,000100 ..... ..... ..... 00110 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Shift Left Word,,,,, +714,vspltb,258,000100 ..... /.... ..... 01000 001100,VX7,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Splat Byte,,,,, +715,vsplth,258,000100 ..... //... ..... 01001 001100,VX6,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Splat Halfword,,,,, +716,vspltisb,259,000100 ..... ..... ///// 01100 001100,VX12,VX,,,,,,VR,,,,,,,I,v2.03,,,Vector Splat Immediate Signed Byte,,,,, +717,vspltish,259,000100 ..... ..... ///// 01101 001100,VX12,VX,,,,,,VR,,,,,,,I,v2.03,,,Vector Splat Immediate Signed Halfword,,,,, +718,vspltisw,259,000100 ..... ..... ///// 01110 001100,VX12,VX,,,,,,VR,,,,,,,I,v2.03,,,Vector Splat Immediate Signed Word,,,,, +719,vspltw,258,000100 ..... ///.. ..... 01010 001100,VX5,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Splat Word,,,,, +720,vsr,264,000100 ..... ..... ..... 01011 000100,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v2.03,,,Vector Shift Right,,,,, +721,vsrab,318,000100 ..... ..... ..... 01100 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Shift Right Algebraic Byte,,,,, +722,vsrad,318,000100 ..... ..... ..... 01111 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Shift Right Algebraic Doubleword,,,,, +723,vsrah,318,000100 ..... ..... ..... 01101 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Shift Right Algebraic Halfword,,,,, +724,vsraw,318,000100 ..... ..... ..... 01110 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Shift Right Algebraic Word,,,,, +725,vsrb,317,000100 ..... ..... ..... 01000 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Shift Right Byte,,,,, +726,vsrd,317,000100 ..... ..... ..... 11011 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Shift Right Doubleword,,,,, +727,vsrh,317,000100 ..... ..... ..... 01001 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Shift Right Halfword,,,,, +728,vsro,264,000100 ..... ..... ..... 10001 001100,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v2.03,,,Vector Shift Right by Octet,,,,, +729,vsrv,265,000100 ..... ..... ..... 11100 000100,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v3.0,,,Vector Shift Right Variable,,,,, +730,vsrw,317,000100 ..... ..... ..... 01010 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Shift Right Word,,,,, +731,vsubcuq,279,000100 ..... ..... ..... 10101 000000,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Subtract & write Carry Unsigned Quadword,,,,, +732,vsubcuw,275,000100 ..... ..... ..... 10110 000000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Subtract & Write Carry-Out Unsigned Word,,,,, +733,vsubfp,321,000100 ..... ..... ..... 00001 001010,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Subtract Floating-Point,,,,, +734,vsubsbs,275,000100 ..... ..... ..... 11100 000000,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Subtract Signed Byte Saturate,,,,, +735,vsubshs,275,000100 ..... ..... ..... 11101 000000,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Subtract Signed Halfword Saturate,,,,, +736,vsubsws,276,000100 ..... ..... ..... 11110 000000,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Subtract Signed Word Saturate,,,,, +737,vsububm,277,000100 ..... ..... ..... 10000 000000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Subtract Unsigned Byte Modulo,,,,, +738,vsububs,278,000100 ..... ..... ..... 11000 000000,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Subtract Unsigned Byte Saturate,,,,, +739,vsubudm,277,000100 ..... ..... ..... 10011 000000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.07,,,Vector Subtract Unsigned Doubleword Modulo,,,,, +740,vsubuhm,277,000100 ..... ..... ..... 10001 000000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Subtract Unsigned Halfword Modulo,,,,, +741,vsubuhs,278,000100 ..... ..... ..... 11001 000000,VX17,VX,,,,,,,,,,,,,I,v2.03,,,Vector Subtract Unsigned Halfword Saturate,,,,, +742,vsubuqm,279,000100 ..... ..... ..... 10100 000000,VX17,VX,,VR,VR,,MSR,VR,,,,,,,I,v2.07,,,Vector Subtract Unsigned Quadword Modulo,,,,, +743,vsubuwm,277,000100 ..... ..... ..... 10010 000000,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Subtract Unsigned Word Modulo,,,,, +744,vsubuws,278,000100 ..... ..... ..... 11010 000000,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Subtract Unsigned Word Saturate,,,,, +745,vsum2sws,290,000100 ..... ..... ..... 11010 001000,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Sum across Half Signed Word Saturate,,,,, +746,vsum4sbs,291,000100 ..... ..... ..... 11100 001000,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Sum across Quarter Signed Byte Saturate,,,,, +747,vsum4shs,291,000100 ..... ..... ..... 11001 001000,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Sum across Quarter Signed Halfword Saturate,,,,, +748,vsum4ubs,292,000100 ..... ..... ..... 11000 001000,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Sum across Quarter Unsigned Byte Saturate,,,,, +749,vsumsws,290,000100 ..... ..... ..... 11110 001000,VX17,VX,,VR,VR,,,VR,VSCR,,,,,,I,v2.03,,,Vector Sum across Signed Word Saturate,,,,, +750,vupkhpx,253,000100 ..... ///// ..... 01101 001110,VX4,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Unpack High Pixel,,,,, +751,vupkhsb,254,000100 ..... ///// ..... 01000 001110,VX4,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Unpack High Signed Byte,,,,, +752,vupkhsh,254,000100 ..... ///// ..... 01001 001110,VX4,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Unpack High Signed Halfword,,,,, +753,vupkhsw,254,000100 ..... ///// ..... 11001 001110,VX4,VX,,,VR,,,VR,,,,,,,I,v2.07,,,Vector Unpack High Signed Word,,,,, +754,vupklpx,253,000100 ..... ///// ..... 01111 001110,VX4,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Unpack Low Pixel,,,,, +755,vupklsb,254,000100 ..... ///// ..... 01010 001110,VX4,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Unpack Low Signed Byte,,,,, +756,vupklsh,254,000100 ..... ///// ..... 01011 001110,VX4,VX,,,VR,,,VR,,,,,,,I,v2.03,,,Vector Unpack Low Signed Halfword,,,,, +757,vupklsw,254,000100 ..... ///// ..... 11011 001110,VX4,VX,,,VR,,,VR,,,,,,,I,v2.07,,,Vector Unpack Low Signed Word,,,,, +758,vxor,313,000100 ..... ..... ..... 10011 000100,VX17,VX,,VR,VR,,,VR,,,,,,,I,v2.03,,,Vector Logical XOR,,,,, +759,wait,876,011111 ///.. ///// ///// 00000 11110/,X13,X,,,,,,,,,,,,,II,v3.0,,,Wait for Interrupt,X,,,, +760,xnop,93,011010 00000 00000 00000 00000 000000,D6,D,,,,,,,,,,,,,I,v2.05,,,Executed No Operation,X,,,, +761,xor[.],94,011111 ..... ..... ..... 01001 11100.,X68,X,,,GPR,GPR,,GPR,CR0,,,,,,I,P1,,SR,XOR,,,Y,,Y +762,xori,93,011010 ..... ..... ..... ..... ......,D6,D,,,,GPR,,GPR,,,,,,,I,P1,,,XOR Immediate,,,Y,,Y +763,xoris,93,011011 ..... ..... ..... ..... ......,D6,D,,,,GPR,,GPR,,,,,,,I,P1,,,XOR Immediate Shifted,,,Y,,Y +764,xsabsdp,512,111100 ..... ///// ..... 10101 1001..,XX2_4,XX2,,,VSR,,MSR,VSR,,,,,,,I,v2.06,,,VSX Scalar Absolute Double-Precision,,,,, +765,xsabsqp,512,111111 ..... 00000 ..... 11001 00100/,X90,X,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Scalar Absolute Quad-Precision,,,,, +766,xsadddp,513,111100 ..... ..... ..... 00100 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Add Double-Precision,,,,, +767,xsaddsp,518,111100 ..... ..... ..... 00000 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Add Single-Precision,,,,, +768,xscmpexpdp,522,111100 ...// ..... ..... 00111 011../,XX3_1,XX3,,VSR,VSR,,MSR,CR,FPSCR,,,,,,I,v3.0,,,VSX Scalar Compare Exponents Double-Precision,,,,, +769,xscmpexpqp,523,111111 ...// ..... ..... 00101 00100/,X28,X,,VSR,VSR,,MSR,CR,FPSCR,,,,,,I,v3.0,,,VSX Scalar Compare Exponents Quad-Precision,,,,, +770,xscmpodp,527,111100 ...// ..... ..... 00101 011../,XX3_1,XX3,,VSR,VSR,,FPSCR,CR,FPSCR,,,,,,I,v2.06,,,VSX Scalar Compare Ordered Double-Precision,,,,, +771,xscmpudp,530,111100 ...// ..... ..... 00100 011../,XX3_1,XX3,,VSR,VSR,,,CR,FPSCR,,,,,,I,v2.06,,,VSX Scalar Compare Unordered Double-Precision,,,,, +772,xscmpuqp,532,111111 ...// ..... ..... 10100 00100/,X28,X,,VSR,VSR,,MSR,CR,FPSCR,,,,,,I,v3.0,,,VSX Scalar Compare Unordered Quad-Precision,,,,, +773,xscpsgndp,533,111100 ..... ..... ..... 10110 000...,XX3_5,XX3,,VSR,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Scalar Copy Sign Double-Precision,,,,, +774,xscpsgnqp,533,111111 ..... ..... ..... 00011 00100/,X93,X,,VSR,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Scalar Copy Sign Quad-Precision,,,,, +775,xscvdphp,534,111100 ..... 10001 ..... 10101 1011..,XX2_4,XX2,,,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Convert with round Double-Precision to Half-Precision format,,,,, +776,xscvdpqp,535,111111 ..... 10110 ..... 11010 00100/,X90,X,,,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Convert Double-Precision to Quad-Precision format,,,,, +777,xscvdpsp,536,111100 ..... ///// ..... 10000 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Convert with round Double-Precision to Single-Precision format,,,,, +778,xscvdpspn,537,111100 ..... ///// ..... 10000 1011..,XX2_4,XX2,,,VSR,,,VSR,,,,,,,I,v2.07,,,VSX Scalar Convert Double-Precision to Single-Precision Non-signalling format,,,,, +779,xscvdpsxds,537,111100 ..... ///// ..... 10101 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Convert with round to zero Double-Precision to Signed Doubleword format,,,,, +780,xscvdpsxws,540,111100 ..... ///// ..... 00101 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Convert with round to zero Double-Precision to Signed Word format,,,,, +781,xscvdpuxds,542,111100 ..... ///// ..... 10100 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Convert with round to zero Double-Precision to Unsigned Doubleword format,,,,, +782,xscvdpuxws,544,111100 ..... ///// ..... 00100 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Convert with round to zero Double-Precision to Unsigned Word format,,,,, +783,xscvhpdp,546,111100 ..... 10000 ..... 10101 1011..,XX2_4,XX2,,,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Convert Half-Precision to Double-Precision format,,,,, +784,xscvqpdp[o],547,111111 ..... 10100 ..... 11010 00100.,X91,X,,,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Convert with round Quad-Precision to Double-Precision format [with round to Odd],,,,, +785,xscvqpsdz,548,111111 ..... 11001 ..... 11010 00100/,X90,X,,,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Convert with round to zero Quad-Precision to Signed Doubleword format,,,,, +786,xscvqpswz,550,111111 ..... 01001 ..... 11010 00100/,X90,X,,,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Convert with round to zero Quad-Precision to Signed Word format,,,,, +787,xscvqpudz,552,111111 ..... 10001 ..... 11010 00100/,X90,X,,,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Convert with round to zero Quad-Precision to Unsigned Doubleword format,,,,, +788,xscvqpuwz,554,111111 ..... 00001 ..... 11010 00100/,X90,X,,,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Convert with round to zero Quad-Precision to Unsigned Word format,,,,, +789,xscvsdqp,556,111111 ..... 01010 ..... 11010 00100/,X90,X,,,VSR,,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Convert Signed Doubleword to Quad-Precision format,,,,, +790,xscvspdp,557,111100 ..... ///// ..... 10100 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Convert Single-Precision to Double-Precision format,,,,, +791,xscvspdpn,558,111100 ..... ///// ..... 10100 1011..,XX2_4,XX2,,,VSR,,,VSR,,,,,,,I,v2.07,,,VSX Scalar Convert Single-Precision to Double-Precision Non-signalling format,,,,, +792,xscvsxddp,559,111100 ..... ///// ..... 10111 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Convert with round Signed Doubleword to Double-Precision format,,,,, +793,xscvsxdsp,559,111100 ..... ///// ..... 10011 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Convert with round Signed Doubleword to Single-Precision format,,,,, +794,xscvudqp,560,111111 ..... 00010 ..... 11010 00100/,X90,X,,,VSR,,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Convert Unsigned Doubleword to Quad-Precision format,,,,, +795,xscvuxddp,561,111100 ..... ///// ..... 10110 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Convert with round Unsigned Doubleword to Double-Precision format,,,,, +796,xscvuxdsp,561,111100 ..... ///// ..... 10010 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Convert with round Unsigned Doubleword to Single-Precision format,,,,, +797,xsdivdp,562,111100 ..... ..... ..... 00111 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Divide Double-Precision,,X,,, +798,xsdivsp,566,111100 ..... ..... ..... 00011 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Divide Single-Precision,,X,,, +799,xsiexpdp,568,111100 ..... ..... ..... 11100 10110.,X84,XX1,,,GPR,GPR,MSR,VSR,,,,,,,I,v3.0,,,VSX Scalar Insert Exponent Double-Precision,,,,, +800,xsiexpqp,569,111111 ..... ..... ..... 11011 00100/,X93,X,,VSR,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Scalar Insert Exponent Quad-Precision,,,,, +801,xsmaxdp,579,111100 ..... ..... ..... 10100 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Scalar Maximum Double-Precision,,,,, +802,xsmindp,585,111100 ..... ..... ..... 10101 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Scalar Minimum Double-Precision,,,,, +803,xsmuldp,600,111100 ..... ..... ..... 00110 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Multiply Double-Precision,,,,, +804,xsmulsp,604,111100 ..... ..... ..... 00010 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Multiply Single-Precision,,,,, +805,xsnabsdp,606,111100 ..... ///// ..... 10110 1001..,XX2_4,XX2,,,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Scalar Negative Absolute Double-Precision,,,,, +806,xsnabsqp,606,111111 ..... 01000 ..... 11001 00100/,X90,X,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Scalar Negative Absolute Quad-Precision,,,,, +807,xsnegdp,607,111100 ..... ///// ..... 10111 1001..,XX2_4,XX2,,,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Scalar Negate Double-Precision,,,,, +808,xsnegqp,607,111111 ..... 10000 ..... 11001 00100/,X90,X,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Scalar Negate Quad-Precision,,,,, +809,xsrdpi,628,111100 ..... ///// ..... 00100 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Round Double-Precision to Integral,,,,, +810,xsrdpic,629,111100 ..... ///// ..... 00110 1011..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Round Double-Precision to Integral using Current rounding mode,,,,, +811,xsrdpim,630,111100 ..... ///// ..... 00111 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Round Double-Precision to Integral toward -Infinity,,,,, +812,xsrdpip,630,111100 ..... ///// ..... 00110 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Round Double-Precision to Integral toward +Infinity,,,,, +813,xsrdpiz,631,111100 ..... ///// ..... 00101 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Round Double-Precision to Integral toward Zero,,,,, +814,xsredp,632,111100 ..... ///// ..... 00101 1010..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Reciprocal Estimate Double-Precision,,,,, +815,xsresp,633,111100 ..... ///// ..... 00001 1010..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Reciprocal Estimate Single-Precision,,,,, +816,xsrqpi[x],634,111111 ..... ////. ..... ..000 00101.,Z23_9,X,,,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Round Quad-Precision to Integral [Exact],,,,, +817,xsrqpxp,636,111111 ..... ////. ..... ..001 00101/,Z23_8,X,,,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Round Quad-Precision to XP,,,,, +818,xsrsp,638,111100 ..... ///// ..... 10001 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Round Double-Precision to Single-Precision,,,,, +819,xsrsqrtedp,639,111100 ..... ///// ..... 00100 1010..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Reciprocal Square Root Estimate Double-Precision,,,,, +820,xsrsqrtesp,640,111100 ..... ///// ..... 00000 1010..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Reciprocal Square Root Estimate Single-Precision,,,,, +821,xssqrtdp,641,111100 ..... ///// ..... 00100 1011..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Square Root Double-Precision,,,,, +822,xssqrtqp[o],642,111111 ..... 11011 ..... 11001 00100.,X91,X,,,VSR,FPSCR,MSR,VSR,FPSCR,FPSCR,,,,,I,v3.0,,,VSX Scalar Square Root Quad-Precision [with round to Odd],,,,, +823,xssqrtsp,644,111100 ..... ///// ..... 00000 1011..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Square Root Single-Precision,,,,, +824,xssubdp,645,111100 ..... ..... ..... 00101 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.06,,,VSX Scalar Subtract Double-Precision,,,,, +825,xssubsp,649,111100 ..... ..... ..... 00001 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,FPSCR,,,,,I,v2.07,,,VSX Scalar Subtract Single-Precision,,,,, +826,xstdivdp,651,111100 ...// ..... ..... 00111 101../,XX3_1,XX3,,VSR,VSR,,,VSR,CR,,,,,,I,v2.06,,,VSX Scalar Test for software Divide Double-Precision,,X,,, +827,xstsqrtdp,652,111100 ...// ///// ..... 00110 1010./,XX2_1,XX2,,VSR,VSR,,,CR,,,,,,,I,v2.06,,,VSX Scalar Test for software Square Root Double-Precision,,,,, +828,xststdcdp,653,111100 ..... ..... ..... 10110 1010./,XX2_2,XX2,,,VSR,,MSR,CR,FPSCR,,,,,,I,v3.0,,,VSX Scalar Test Data Class Double-Precision,,,,, +829,xststdcqp,654,111111 ..... ..... ..... 10110 00100/,X31,X,,,VSR,,MSR,CR,FPSCR,,,,,,I,v3.0,,,VSX Scalar Test Data Class Quad-Precision,,,,, +830,xststdcsp,655,111100 ..... ..... ..... 10010 1010./,XX2_2,XX2,,,VSR,,MSR,CR,FPSCR,,,,,,I,v3.0,,,VSX Scalar Test Data Class Single-Precision,,,,, +831,xsxexpdp,656,111100 ..... 00000 ..... 10101 1011./,XX2_3,XX2,,,VSR,,MSR,GPR,,,,,,,I,v3.0,,,VSX Scalar Extract Exponent Double-Precision,,,,, +832,xsxexpqp,656,111111 ..... 00010 ..... 11001 00100/,X90,X,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Scalar Extract Exponent Quad-Precision,,,,, +833,xsxsigdp,657,111100 ..... 00001 ..... 10101 1011./,XX2_3,XX2,,,,,,,,,,,,,I,v3.0,,,VSX Scalar Extract Significand Double-Precision,,,,, +834,xsxsigqp,657,111111 ..... 10010 ..... 11001 00100/,X90,X,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Scalar Extract Significand Quad-Precision,,,,, +835,xvabsdp,658,111100 ..... ///// ..... 11101 1001..,XX2_4,XX2,,,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Vector Absolute Double-Precision,,,,, +836,xvabssp,658,111100 ..... ///// ..... 11001 1001..,XX2_4,XX2,,,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Vector Absolute Single-Precision,,,,, +837,xvadddp,659,111100 ..... ..... ..... 01100 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Add Double-Precision,,,,, +838,xvaddsp,663,111100 ..... ..... ..... 01000 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Add Single-Precision,,,,, +839,xvcmpeqdp[.],665,111100 ..... ..... ..... .1100 011...,XX3_4,XX3,,VSR,VSR,,FPSCR,VSR,CR,,,,,,I,v2.06,,,VSX Vector Compare Equal Double-Precision,,,,, +840,xvcmpeqsp[.],666,111100 ..... ..... ..... .1000 011...,XX3_4,XX3,,VSR,VSR,,FPSCR,VSR,CR,,,,,,I,v2.06,,,VSX Vector Compare Equal Single-Precision,,,,, +841,xvcmpgedp[.],667,111100 ..... ..... ..... .1110 011...,XX3_4,XX3,,VSR,VSR,,FPSCR,VSR,CR,,,,,,I,v2.06,,,VSX Vector Compare Greater Than or Equal Double-Precision,,,,, +842,xvcmpgesp[.],668,111100 ..... ..... ..... .1010 011...,XX3_4,XX3,,VSR,VSR,,FPSCR,VSR,CR,,,,,,I,v2.06,,,VSX Vector Compare Greater Than or Equal Single-Precision,,,,, +843,xvcmpgtdp[.],669,111100 ..... ..... ..... .1101 011...,XX3_4,XX3,,VSR,VSR,,FPSCR,VSR,CR,,,,,,I,v2.06,,,VSX Vector Compare Greater Than Double-Precision,,,,, +844,xvcmpgtsp[.],670,111100 ..... ..... ..... .1001 011...,XX3_4,XX3,,VSR,VSR,,FPSCR,VSR,CR,,,,,,I,v2.06,,,VSX Vector Compare Greater Than Single-Precision,,,,, +845,xvcpsgndp,671,111100 ..... ..... ..... 11110 000...,XX3_5,XX3,,VSR,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Vector Copy Sign Double-Precision,,,,, +846,xvcpsgnsp,671,111100 ..... ..... ..... 11010 000...,XX3_5,XX3,,VSR,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Vector Copy Sign Single-Precision,,,,, +847,xvcvdpsp,672,111100 ..... ///// ..... 11000 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Convert with round Double-Precision to Single-Precision format,,,,, +848,xvcvdpsxds,673,111100 ..... ///// ..... 11101 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Convert with round to zero Double-Precision to Signed Doubleword format,,,,, +849,xvcvdpsxws,675,111100 ..... ///// ..... 01101 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Convert with round to zero Double-Precision to Signed Word format,,,,, +850,xvcvdpuxds,677,111100 ..... ///// ..... 11100 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Convert with round to zero Double-Precision to Unsigned Doubleword format,,,,, +851,xvcvdpuxws,679,111100 ..... ///// ..... 01100 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Convert with round to zero Double-Precision to Unsigned Word format,,,,, +852,xvcvhpsp,681,111100 ..... 11000 ..... 11101 1011..,XX2_4,XX2,,,VSR,FPSCR,MSR,VSR,FPSCR,,,,,,I,v3.0,,,VSX Vector Convert Half-Precision to Single-Precision format,,,,, +853,xvcvspdp,682,111100 ..... ///// ..... 11100 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Convert Single-Precision to Double-Precision format,,,,, +854,xvcvsphp,683,111100 ..... 11001 ..... 11101 1011..,XX2_4,XX2,,,VSR,FPSCR,MSR,VSR,FPSCR,,,,,,I,v3.0,,,VSX Vector Convert with round Single-Precision to Half-Precision format,,,,, +855,xvcvspsxds,684,111100 ..... ///// ..... 11001 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Convert with round to zero Single-Precision to Signed Doubleword format,,,,, +856,xvcvspsxws,686,111100 ..... ///// ..... 01001 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Convert with round to zero Single-Precision to Signed Word format,,,,, +857,xvcvspuxds,688,111100 ..... ///// ..... 11000 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Convert with round to zero Single-Precision to Unsigned Doubleword format,,,,, +858,xvcvspuxws,690,111100 ..... ///// ..... 01000 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Convert with round to zero Single-Precision to Unsigned Word format,,,,, +859,xvcvsxddp,692,111100 ..... ///// ..... 11111 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Convert with round Signed Doubleword to Double-Precision format,,,,, +860,xvcvsxdsp,692,111100 ..... ///// ..... 11011 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Convert with round Signed Doubleword to Single-Precision format,,,,, +861,xvcvsxwdp,693,111100 ..... ///// ..... 01111 1000..,XX2_4,XX2,,,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Vector Convert Signed Word to Double-Precision format,,,,, +862,xvcvsxwsp,693,111100 ..... ///// ..... 01011 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Convert with round Signed Word to Single-Precision format,,,,, +863,xvcvuxddp,694,111100 ..... ///// ..... 11110 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Convert with round Unsigned Doubleword to Double-Precision format,,,,, +864,xvcvuxdsp,694,111100 ..... ///// ..... 11010 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Convert with round Unsigned Doubleword to Single-Precision format,,,,, +865,xvcvuxwdp,695,111100 ..... ///// ..... 01110 1000..,XX2_4,XX2,,,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Vector Convert Unsigned Word to Double-Precision format,,,,, +866,xvcvuxwsp,695,111100 ..... ///// ..... 01010 1000..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Convert with round Unsigned Word to Single-Precision format,,,,, +867,xvdivdp,696,111100 ..... ..... ..... 01111 000...,XX3_5,XX3,,,,,,,,,,,,,I,v2.06,,,VSX Vector Divide Double-Precision,,X,,, +868,xvdivsp,698,111100 ..... ..... ..... 01011 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Divide Single-Precision,,X,,, +869,xviexpdp,700,111100 ..... ..... ..... 11111 000...,XX3_5,XX3,,VSR,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Insert Exponent Double-Precision,,,,, +870,xviexpsp,700,111100 ..... ..... ..... 11011 000...,XX3_5,XX3,,VSR,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Insert Exponent Single-Precision,,,,, +871,xvmaddmdp,701,111100 ..... ..... ..... 01101 001...,XX3_5,XX3,,,,,,,,,,,,,I,v2.06,,,VSX Vector Multiply-Add Type-M Double-Precision,,,,, +872,xvmaxdp,707,111100 ..... ..... ..... 11100 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Maximum Double-Precision,,,,, +873,xvmaxsp,709,111100 ..... ..... ..... 11000 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Maximum Single-Precision,,,,, +874,xvmindp,711,111100 ..... ..... ..... 11101 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Minimum Double-Precision,,,,, +875,xvminsp,713,111100 ..... ..... ..... 11001 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Minimum Single-Precision,,,,, +876,xvmsubmsp,718,111100 ..... ..... ..... 01011 001...,XX3_5,XX3,,,,,,,,,,,,,I,v2.06,,,VSX Vector Multiply-Subtract Type-M Single-Precision,,,,, +877,xvmuldp,721,111100 ..... ..... ..... 01110 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Multiply Double-Precision,,,,, +878,xvmulsp,723,111100 ..... ..... ..... 01010 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Multiply Single-Precision,,,,, +879,xvnabsdp,725,111100 ..... ///// ..... 11110 1001..,XX2_4,XX2,,,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Vector Negative Absolute Double-Precision,,,,, +880,xvnabssp,725,111100 ..... ///// ..... 11010 1001..,XX2_4,XX2,,,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Vector Negative Absolute Single-Precision,,,,, +881,xvnegdp,726,111100 ..... ///// ..... 11111 1001..,XX2_4,XX2,,,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Vector Negate Double-Precision,,,,, +882,xvnegsp,726,111100 ..... ///// ..... 11011 1001..,XX2_4,XX2,,,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Vector Negate Single-Precision,,,,, +883,xvrdpi,741,111100 ..... ///// ..... 01100 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Round Double-Precision to Integral,,,,, +884,xvrdpic,741,111100 ..... ///// ..... 01110 1011..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Round Double-Precision to Integral using Current rounding mode,,,,, +885,xvrdpim,742,111100 ..... ///// ..... 01111 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Round Double-Precision to Integral toward -Infinity,,,,, +886,xvrdpip,742,111100 ..... ///// ..... 01110 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Round Double-Precision to Integral toward +Infinity,,,,, +887,xvrdpiz,743,111100 ..... ///// ..... 01101 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Round Double-Precision to Integral toward Zero,,,,, +888,xvredp,744,111100 ..... ///// ..... 01101 1010..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Reciprocal Estimate Double-Precision,,,,, +889,xvresp,745,111100 ..... ///// ..... 01001 1010..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Reciprocal Estimate Single-Precision,,,,, +890,xvrspi,746,111100 ..... ///// ..... 01000 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Round Single-Precision to Integral,,,,, +891,xvrspic,746,111100 ..... ///// ..... 01010 1011..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Round Single-Precision to Integral using Current rounding mode,,,,, +892,xvrspim,747,111100 ..... ///// ..... 01011 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Round Single-Precision to Integral toward -Infinity,,,,, +893,xvrspip,747,111100 ..... ///// ..... 01010 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Round Single-Precision to Integral toward +Infinity,,,,, +894,xvrspiz,748,111100 ..... ///// ..... 01001 1001..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Round Single-Precision to Integral toward Zero,,,,, +895,xvrsqrtedp,748,111100 ..... ///// ..... 01100 1010..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Reciprocal Square Root Estimate Double-Precision,,,,, +896,xvrsqrtesp,750,111100 ..... ///// ..... 01000 1010..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Reciprocal Square Root Estimate Single-Precision,,,,, +897,xvsqrtdp,751,111100 ..... ///// ..... 01100 1011..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Square Root Double-Precision,,,,, +898,xvsqrtsp,752,111100 ..... ///// ..... 01000 1011..,XX2_4,XX2,,,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Square Root Single-Precision,,,,, +899,xvsubdp,753,111100 ..... ..... ..... 01101 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Subtract Double-Precision,,,,, +900,xvsubsp,755,111100 ..... ..... ..... 01001 000...,XX3_5,XX3,,VSR,VSR,,FPSCR,VSR,FPSCR,,,,,,I,v2.06,,,VSX Vector Subtract Single-Precision,,,,, +901,xvtdivdp,757,111100 ...// ..... ..... 01111 101../,XX3_1,XX3,,VSR,VSR,,,CR,,,,,,,I,v2.06,,,VSX Vector Test for software Divide Double-Precision,,X,,, +902,xvtdivsp,758,111100 ...// ..... ..... 01011 101../,XX3_1,XX3,,VSR,VSR,,,CR,,,,,,,I,v2.06,,,VSX Vector Test for software Divide Single-Precision,,X,,, +903,xvtsqrtdp,759,111100 ...// ///// ..... 01110 1010./,XX2_1,XX2,,,VSR,,,CR,,,,,,,I,v2.06,,,VSX Vector Test for software Square Root Double-Precision,,,,, +904,xvtsqrtsp,759,111100 ...// ///// ..... 01010 1010./,XX2_1,XX2,,,VSR,,,CR,,,,,,,I,v2.06,,,VSX Vector Test for software Square Root Single-Precision,,,,, +905,xvtstdcdp,760,111100 ..... ..... ..... 1111. 101...,XX2_7,XX2,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Test Data Class Double-Precision,,,,, +906,xvtstdcsp,761,111100 ..... ..... ..... 1101. 101...,XX2_7,XX2,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Test Data Class Single-Precision,,,,, +907,xvxexpdp,762,111100 ..... 00000 ..... 11101 1011..,XX2_4,XX2,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Extract Exponent Double-Precision,,,,, +908,xvxexpsp,762,111100 ..... 01000 ..... 11101 1011..,XX2_4,XX2,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Extract Exponent Single-Precision,,,,, +909,xvxsigdp,763,111100 ..... 00001 ..... 11101 1011..,XX2_4,XX2,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Extract Significand Double-Precision,,,,, +910,xvxsigsp,763,111100 ..... 01001 ..... 11101 1011..,XX2_4,XX2,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Extract Significand Single-Precision,,,,, +911,xxbrd,764,111100 ..... 10111 ..... 11101 1011..,XX2_4,XX2,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Byte-Reverse Doubleword,,,,, +912,xxbrh,764,111100 ..... 00111 ..... 11101 1011..,XX2_4,XX2,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Byte-Reverse Halfword,,,,, +913,xxbrq,765,111100 ..... 11111 ..... 11101 1011..,XX2_4,XX2,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Byte-Reverse Quadword,,,,, +914,xxbrw,765,111100 ..... 01111 ..... 11101 1011..,XX2_4,XX2,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Byte-Reverse Word,,,,, +915,xxextractuw,766,111100 ..... /.... ..... 01010 0101..,XX2_6,XX2,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Extract Unsigned Word,,,,, +916,xxinsertw,766,111100 ..... /.... ..... 01011 0101..,XX2_6,XX2,,,VSR,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Insert Word,,,,, +917,xxland,767,111100 ..... ..... ..... 10000 010...,XX3_5,XX3,,VSR,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Vector Logical AND,,,,, +918,xxlandc,767,111100 ..... ..... ..... 10001 010...,XX3_5,XX3,,VSR,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Vector Logical AND with Complement,,,,, +919,xxleqv,768,111100 ..... ..... ..... 10111 010...,XX3_5,XX3,,VSR,VSR,,,VSR,,,,,,,I,v2.07,,,VSX Vector Logical Equivalence,,,,, +920,xxlnand,768,111100 ..... ..... ..... 10110 010...,XX3_5,XX3,,VSR,VSR,,,VSR,,,,,,,I,v2.07,,,VSX Vector Logical NAND,,,,, +921,xxlnor,769,111100 ..... ..... ..... 10100 010...,XX3_5,XX3,,VSR,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Vector Logical NOR,,,,, +922,xxlor,770,111100 ..... ..... ..... 10010 010...,XX3_5,XX3,,VSR,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Vector Logical OR,,,,, +923,xxlorc,769,111100 ..... ..... ..... 10101 010...,XX3_5,XX3,,VSR,VSR,,,VSR,,,,,,,I,v2.07,,,VSX Vector Logical OR with Complement,,,,, +924,xxlxor,770,111100 ..... ..... ..... 10011 010...,XX3_5,XX3,,VSR,VSR,,,VSR,,,,,,,I,v2.06,,,VSX Vector Logical XOR,,,,, +925,xxmrghw,771,111100 ..... ..... ..... 00010 010...,XX3_5,XX3,,VSR,VSR,,MSR,VSR,,,,,,,I,v2.06,,,VSX Vector Merge Word High,,,,, +926,xxmrglw,771,111100 ..... ..... ..... 00110 010...,XX3_5,XX3,,VSR,VSR,,MSR,VSR,,,,,,,I,v2.06,,,VSX Vector Merge Word Low,,,,, +927,xxpermdi,773,111100 ..... ..... ..... 0..01 010...,XX3_2,XX3,,VSR,VSR,,MSR,VSR,,,,,,,I,v2.06,,,VSX Vector Doubleword Permute Immediate,,,,, +928,xxsldwi,774,111100 ..... ..... ..... 0..00 010...,XX3_3,XX3,,VSR,VSR,,MSR,VSR,,,,,,,I,v2.06,,,VSX Vector Shift Left Double by Word Immediate,,,,, +929,xxspltib,774,111100 ..... 00... ..... 01011 01000.,X82,XX1,,,,,MSR,VSR,,,,,,,I,v3.0,,,VSX Vector Splat Immediate Byte,,,,, +930,xxspltw,774,111100 ..... ///.. ..... 01010 0100..,XX2_5,XX2,,,VSR,,MSR,VSR,,,,,,,I,v2.06,,,VSX Vector Splat Word,,,,, \ No newline at end of file diff --git a/tests/Tests/Example/Project.hs b/tests/Tests/Example/Project.hs new file mode 100644 index 0000000..51c5907 --- /dev/null +++ b/tests/Tests/Example/Project.hs @@ -0,0 +1,24 @@ +module Tests.Example.Project where + +import Prelude + +import Test.Tasty +import Test.Tasty.TH +import Test.Tasty.Hedgehog + +import Hedgehog ((===)) +import qualified Hedgehog as H +import qualified Hedgehog.Gen as Gen +import qualified Hedgehog.Range as Range + +prop_plusIsCommutative :: H.Property +prop_plusIsCommutative = H.property $ do + a <- H.forAll (Gen.integral (Range.linear minBound maxBound)) + b <- H.forAll (Gen.integral (Range.linear minBound maxBound)) + plus a b === plus b a + +tests :: TestTree +tests = $(testGroupGenerator) + +main :: IO () +main = defaultMain tests diff --git a/tests/doctests.hs b/tests/doctests.hs new file mode 100644 index 0000000..35e40fb --- /dev/null +++ b/tests/doctests.hs @@ -0,0 +1,20 @@ +module Main where + +import Prelude +import Build_doctests (flags, pkgs, module_sources) +import Test.DocTest (doctest) +import System.Environment (lookupEnv) +import System.Process + +getGlobalPackageDb :: IO String +getGlobalPackageDb = readProcess "ghc" ["--print-global-package-db"] "" + +main :: IO () +main = do + inNixShell <-lookupEnv "IN_NIX_SHELL" + extraFlags <- + case inNixShell of + Nothing -> pure [] + Just _ -> pure . ("-package-db="++) <$> getGlobalPackageDb + + doctest (flags ++ extraFlags ++ pkgs ++ module_sources) diff --git a/tests/unittests.hs b/tests/unittests.hs new file mode 100644 index 0000000..bb3fa79 --- /dev/null +++ b/tests/unittests.hs @@ -0,0 +1,10 @@ +import Prelude + +import Test.Tasty + +import qualified Tests.Example.Project + +main :: IO () +main = defaultMain $ testGroup "." + [ Tests.Example.Project.tests + ]