prep for notable re-org

hs/Bus.hs

@@ -4,12 +4,12 @@ module Bus() where
 import Clash.Prelude
 
 import Peripherals.Ram(Ram, RamLine, read, RamAddr)
-import Peripherals.Uart(UartAddr, read)
+import Peripherals.Uart(UartAddr, read, write)
 import Machine(Peripherals(..))
 import BusTypes(
     BusError(..),
     TransactionSize(..),
-    Request(..),
+    ReadRequest(..),
     BusResponse(..),
     BusVal(..),
     ReadResponse(..),
@@ -32,18 +32,15 @@ alignCheck addr SizeQuadWord   = addr `mod` 16 == 0
 (uartStart, uartEnd) = (0x10000000 :: Addr, uartStart + 7)
 
 -- reading/writing from/to UART is implemented as reading/writing
--- from/to STDIO, so we need IO.
-read :: Request -> Peripherals -> IO ReadResponse
+-- from/to stdin/stdout, so we need IO.
+read :: ReadRequest -> Peripherals -> IO ReadResponse
 read (Request addr size) peripherals
-  | not (alignCheck addr size) = return $ ReadResponse $ Error UnAligned
+  | not (alignCheck addr size) = return $ Left UnAligned
   | (addr >= ramStart) && (addr <= ramEnd) =
-    return        $
-    ReadResponse  $
-    Result        $ Peripherals.Ram.read size ramAddr (ram peripherals)
+      return $ Right $ Peripherals.Ram.read size ramAddr (ram peripherals)
   | (addr >= uartStart) && (addr <= uartEnd) =
-     ReadResponse . Result <$>
-     Peripherals.Uart.read size uartAddr
-  | otherwise = return $ ReadResponse $ Error UnMapped
+      Right <$> Peripherals.Uart.read size uartAddr
+  | otherwise = return $ Left UnMapped
     where
       ramAddrNoOffset = addr - ramStart
       ramAddr :: RamAddr
@@ -52,3 +49,16 @@ read (Request addr size) peripherals
       uartAddrNoOffset = addr - uartStart
       uartAddr :: UartAddr
       uartAddr = resize uartAddrNoOffset
+
+-- write :: BusVal -> Addr -> Peripherals -> IO WriteResponse
+-- write val addr peripherals
+--   | (addr >= uartStart) && (addr <= uartEnd) =
+--       WriteResponse . Result <$> Peripherals.Uart.write val uartAddr
+--     where
+--       ramAddrNoOffset = addr - ramStart
+--       ramAddr :: RamAddr
+--       ramAddr = resize ramAddrNoOffset
+
+--       uartAddrNoOffset = addr - uartStart
+--       uartAddr :: UartAddr
+--       uartAddr = resize uartAddrNoOffset

hs/BusTypes.hs

@@ -2,7 +2,7 @@
 module BusTypes(
     BusError(..),
     TransactionSize(..),
-    Request(..),
+    ReadRequest(..),
     BusResponse(..),
     BusVal(..),
     ReadResponse(..),
@@ -27,7 +27,7 @@ data TransactionSize
     | SizeQuadWord
     deriving (Generic, Show, Eq, NFDataX)
 
-data Request = Request Addr TransactionSize
+data ReadRequest = Request Addr TransactionSize
     deriving (Generic, Show, Eq, NFDataX)
 
 data BusResponse a
@@ -43,8 +43,10 @@ data BusVal
     | BusQuadWord QuadWord
     deriving (Generic, Show, Eq, NFDataX)
 
-newtype ReadResponse = ReadResponse (BusResponse BusVal)
-    deriving (Generic, Show, Eq, NFDataX)
+-- newtype ReadResponse = ReadResponse (BusResponse BusVal)
+--     deriving (Generic, Show, Eq, NFDataX)
+
+type ReadResponse = Either BusError BusVal
 
 newtype WriteResponse = WriteResponse (BusResponse ())
     deriving (Generic, Show, Eq, NFDataX)

hs/Peripherals/Ram.hs

@@ -85,6 +85,7 @@ readDoubleWordHelper ram addr = bitCoerce $ bitCoerce word0 ++# bitCoerce word1
     word0 = readFullWordHelper ram addr
     word1 = readFullWordHelper ram (addr + 1)
 
+-- write :: BusVal -> UartAddr -> IO ()
 write :: Ram -> RamAddr -> RamLine -> Ram
 write ram addr value = replace addr value ram