Yehowshua/RiscV-Formal
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prep for notable re-org

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Yehowshua Immanuel 2025-02-26 02:24:23 -05:00
parent 024115e389
commit c8b192cade
4 changed files with 31 additions and 18 deletions
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1
hs/Peripherals/Ram.hs
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@ -85,6 +85,7 @@ readDoubleWordHelper ram addr = bitCoerce $ bitCoerce word0 ++# bitCoerce word1
word0 = readFullWordHelper ram addr
word1 = readFullWordHelper ram (addr + 1)
-- write :: BusVal -> UartAddr -> IO ()
write :: Ram -> RamAddr -> RamLine -> Ram
write ram addr value = replace addr value ram

6
hs/Peripherals/Uart.hs
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@ -68,9 +68,9 @@ read size addr
| otherwise = return $ busValFromByte size 0x00
extractLowestByte :: BusVal -> Byte
extractLowestByte (BusByte b) = b
extractLowestByte (BusHalfWord hw) = resize hw
extractLowestByte (BusFullWord fw) = resize fw
extractLowestByte (BusByte b) = b
extractLowestByte (BusHalfWord hw) = resize hw
extractLowestByte (BusFullWord fw) = resize fw
extractLowestByte (BusDoubleWord dw) = resize dw
extractLowestByte (BusQuadWord qw) = resize qw