prune more warnings and re-org Decode files a bit
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Yehowshua Immanuel
parent
67b44dedc0
commit
7f7ba49ee1
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@ -1,60 +1,28 @@
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{-# LANGUAGE DataKinds #-}
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{-# LANGUAGE NumericUnderscores #-}
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module Isa.Decode(decode) where
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import Isa.Forms(
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FUNCT7, RS2, RS1, FUNCT3, RD, OPCODE,
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IMM12, IMM13, IMM20, IMM21,
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module Decode(decode) where
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import DecodeTypes(
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RTypeFields(..), ITypeFields(..), STypeFields(..),
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BTypeFields(..), UTypeFields(..), JTypeFields(..),
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Opcode(..)
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)
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import Clash.Prelude
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import Data.Functor.Contravariant (Op)
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import Types(Mem, Addr, Insn)
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import Distribution.Backpack.FullUnitId (FullDb)
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import Types(Insn)
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getOpcode :: Insn -> Unsigned 7
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getOpcode instr = bitCoerce $ slice d6 d0 (pack instr)
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getImm12 :: Insn -> Unsigned 12
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getImm12 instr = bitCoerce $ slice d31 d20 (pack instr)
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getImm12SType :: Insn -> Unsigned 12
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getImm12SType instr = bitCoerce $ immediateUpper ++# immediateLower
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decode :: Insn -> Opcode
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decode insn =
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decodeRType insn `orElse`
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decodeIType insn `orElse`
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decodeSType insn `orElse`
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decodeBType insn `orElse`
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decodeUType insn `orElse`
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decodeJType insn
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where
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immediateUpper = (slice d31 d25 (pack instr))
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immediateLower = (slice d11 d7 (pack instr))
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getImm20UType :: Insn -> Unsigned 20
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getImm20UType instr = bitCoerce $ slice d31 d12 (pack instr)
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getImm13BType :: Insn -> Unsigned 13
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getImm13BType instr = bitCoerce $ imm12 ++# imm10_5 ++# imm4_1 ++# imm11 ++# zero
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where
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imm12 = slice d31 d31 (pack instr) -- imm[12]
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imm10_5 = slice d30 d25 (pack instr) -- imm[10:5]
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imm4_1 = slice d11 d8 (pack instr) -- imm[4:1]
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imm11 = slice d7 d7 (pack instr) -- imm[11]
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zero = 0 :: BitVector 1 -- LSB always zero for B-type
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getFunct3 :: Insn -> Unsigned 3
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getFunct3 instr = bitCoerce $ slice d14 d12 (pack instr)
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getFunct7 :: Insn -> Unsigned 7
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getFunct7 instr = bitCoerce $ slice d31 d25 (pack instr)
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getRd :: Insn -> Unsigned 5
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getRd instr = bitCoerce $ slice d11 d7 (pack instr)
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getRs2 :: Insn -> Unsigned 5
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getRs2 instr = bitCoerce $ slice d24 d20 (pack instr)
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getRs1 :: Insn -> Unsigned 5
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getRs1 instr = bitCoerce $ slice d19 d15 (pack instr)
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orElse :: Opcode -> Opcode -> Opcode
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orElse Unimplemented y = y
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orElse x _ = x
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decodeRType :: Insn -> Opcode
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decodeRType insn =
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@ -192,15 +160,41 @@ decodeJType insn =
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rd = getRd insn
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imm21 = getImm21JType insn
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orElse :: Opcode -> Opcode -> Opcode
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orElse Unimplemented y = y
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orElse x _ = x
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getOpcode :: Insn -> Unsigned 7
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getOpcode instr = bitCoerce $ slice d6 d0 (pack instr)
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decode :: Insn -> Opcode
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decode insn =
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decodeRType insn `orElse`
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decodeIType insn `orElse`
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decodeSType insn `orElse`
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decodeBType insn `orElse`
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decodeUType insn `orElse`
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decodeJType insn
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getImm12 :: Insn -> Unsigned 12
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getImm12 instr = bitCoerce $ slice d31 d20 (pack instr)
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getImm12SType :: Insn -> Unsigned 12
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getImm12SType instr = bitCoerce $ immediateUpper ++# immediateLower
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where
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immediateUpper = (slice d31 d25 (pack instr))
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immediateLower = (slice d11 d7 (pack instr))
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getImm20UType :: Insn -> Unsigned 20
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getImm20UType instr = bitCoerce $ slice d31 d12 (pack instr)
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getImm13BType :: Insn -> Unsigned 13
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getImm13BType instr = bitCoerce $ imm12 ++# imm10_5 ++# imm4_1 ++# imm11 ++# zero
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where
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imm12 = slice d31 d31 (pack instr) -- imm[12]
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imm10_5 = slice d30 d25 (pack instr) -- imm[10:5]
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imm4_1 = slice d11 d8 (pack instr) -- imm[4:1]
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imm11 = slice d7 d7 (pack instr) -- imm[11]
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zero = 0 :: BitVector 1 -- LSB always zero for B-type
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getFunct3 :: Insn -> Unsigned 3
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getFunct3 instr = bitCoerce $ slice d14 d12 (pack instr)
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getFunct7 :: Insn -> Unsigned 7
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getFunct7 instr = bitCoerce $ slice d31 d25 (pack instr)
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getRd :: Insn -> Unsigned 5
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getRd instr = bitCoerce $ slice d11 d7 (pack instr)
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getRs2 :: Insn -> Unsigned 5
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getRs2 instr = bitCoerce $ slice d24 d20 (pack instr)
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getRs1 :: Insn -> Unsigned 5
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getRs1 instr = bitCoerce $ slice d19 d15 (pack instr)
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@ -1,7 +1,7 @@
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{-# LANGUAGE DataKinds #-}
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{-# LANGUAGE NumericUnderscores #-}
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module Isa.Forms(
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module DecodeTypes(
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FUNCT7, RS2, RS1, FUNCT3, RD, OPCODE,
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IMM12, IMM13, IMM20, IMM21,
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@ -11,7 +11,6 @@ module Isa.Forms(
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Opcode(..)
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) where
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import Clash.Prelude
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import Types(Mem, Addr, Insn)
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type FUNCT7 = Unsigned 7
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type RS2 = Unsigned 5
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@ -20,7 +20,7 @@ import Cpu(
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RISCVCPU(..),
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riscvCPUInit)
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import Fetch(fetchInstruction, FetchResult (..))
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import Isa.Decode(decode)
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import Decode(decode)
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data Args = Args {
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firmware :: FilePath
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@ -87,8 +87,8 @@ library
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exposed-modules:
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Simulation
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other-modules:
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Isa.Decode,
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Isa.Forms,
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Decode,
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DecodeTypes,
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Peripherals.Ram,
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Peripherals.Uart,
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Peripherals.UartCFFI,
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